Read-Only Memories TRIZ Cases

A stacked resistive memory cell array uses a control circuit to identify and access program modes for each layer based on address signals.

NAND memory arrays perform binary neural network inference using series-connected cell pairs for weight storage and voltage pattern inputs.

A charge-trap memory system estimates retention drift using reference cells to adjust read thresholds and maintain data integrity.

Merging EEPROM and Flash matrices into shared supporting circuits reduces chip area and manufacturing costs while enabling independent, parallel data access.

A memory cell isolates its internal source node to clamp gate-to-source voltage near zero volts during array operations.

A memory system adjusts pre-read voltage levels to reduce MSB data error rates during programming operations.

Partial programming reduces peak power consumption and prevents voltage drops during parallel operations in multi-die storage systems.

Independent GIDL tuning for each sub-block compensates for manufacturing variations, ensuring uniform erased threshold voltage distributions.

Detects permanent weak erase failures in solid-state storage devices by comparing erase fail bit metrics against predefined thresholds to isolate defective cells.

A non-volatile memory device activates selection lines simultaneously to drive bit lines with program voltage for multi-page programming.

Parent and child memory structures store classified defective cell addresses to reduce buffer area while maintaining a 100% repair rate.

Variable signal lines in non-volatile memory blocks reduce disturbance influence on data holding characteristics.

Relocating column redundancy fuse blocks to chip edges aligns arrays without detours, reducing occupied area.

Adjusting non-volatile memory programming pulse widths by magnitude to compensate for charge pump recovery limits and narrow threshold voltage distributions.

Detecting natural threshold voltage distributions in NAND flash memory enables targeted pass voltage adjustments during programming operations.

Segmented element isolation structure with protruding portions prevents semiconductor layer remnants, reducing leak currents in field effect transistors.

An internal signal generator blocks command transferal to the operation controller during voltage discharge, preventing read operation malfunctions.

A dynamic on-chip calibration system uses a wordline voltage proxy to adjust memory control signals for improved data retention.

A semiconductor memory device adjusts precharge voltage levels based on the distance between the read and write circuit and selected memory blocks.

Replacing silicon p-n junctions with a symmetric resistive memory material as a rectifier enables programming and erasing operations that exceed 10^6 A/cm2.

A memory device applies a recovery pulse to compensate for charges detrapped from channel areas during program loop suspension.

Controller adjusts status read waiting times based on lower or upper page address to reduce operational load.

A memory controller divides data into error-corrected and non-error-corrected groups to generate optimized data chunks for storage.

An error check and scrub control circuit generates active, read, and write commands to perform automatic error correction operations within semiconductor devices.

Variable pre-verify and main verify voltage differences optimize threshold distribution in semiconductor memory programming operations.

Dynamic bulk voltage control lowers switching MOS transistor thresholds during access, resolving low power trade-offs that delay sensing and amplification.

A memory device operation method sequences erase and program cycles on ground selection and erase control transistors to regulate electrical states.

A semiconductor device with negative differential transconductance determines data values from voltage ranges in a single read operation.

Peripheral circuits program buffer pages with single-level cell data to perform multi-level operations on normal pages, reducing circuit area.

Stacking a peripheral circuit layer below a memory cell array reduces chip size while maintaining high memory capacity.

Source line control circuit monitors total current to adjust voltage levels for accurate threshold determination in semiconductor memory devices.

Discharge circuit uses simultaneous transistor activation to shorten reset time below 200 ns while preventing latchup conditions.

A fuse circuit maintains stable potentials across cut fuses after power-up to ensure accurate state detection.

A nonvolatile memory device uses an encoder to randomize data via logical operations before programming.

Iterative read voltage adjustment minimizes error bits, restoring data reliability despite threshold voltage shifts from program erase cycles.

A source liner contacts the source line region through a sealing layer to prevent bridge formation in three-dimensional memory devices.

A threshold voltage detection circuit decodes logical states in non-volatile memory cells using a multifactor function.

Alternating write pulse polarity prevents tellurium and antimony migration in phase-change material, maintaining data retention during repeated operations.

Flip-flop feedback loops generate synchronized control pulses to stabilize high-speed memory operation against voltage differences.

A nonvolatile memory device adjusts program voltage duration based on verification results for far cells.

A memory quality engine applies cumulative distribution function analysis to evaluate device health and adjust operating parameters.

Disturb detection monitors sector activity and triggers backup operations to prevent non-correctable data invalidation from neighbor cell interference.

A phase change memory cell supports optical and electrical programming modes using a single variable resistor material.

Dual address registers enable concurrent page reading and address transfer, resolving bottlenecks from scattered data across multiple blocks.

Dynamic turn-on adjustment prevents fuse reconnection and leakage by stopping the write operation after voltage detection confirms a stable blown state.

Selective activation of multiple data buffering units enhances driving ability, resolving narrow circuit interval constraints.

Ferroelectric memory elements store multiple bits via remanent polarization, increasing capacity without expanding area.

Valley tracking calibrates read levels from cell counts, reducing errors caused by threshold voltage distribution widening.

A memory device reconfigures write operations to enable concurrent read execution on separate array planes.