Semiconductor Memory Page Buffer Driving Ability
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Semiconductor memory devices face challenges in adjusting driving ability for efficient data output operations, particularly in flash memory devices, where increasing the size of transistors to enhance driving ability is hindered by narrow circuit intervals and limited effectiveness in improving data read operation speed.
Innovation Solution
The semiconductor memory device incorporates a page buffer circuit with multiple data buffering units and a control block that selectively activates these units to form current paths, allowing for data duplication and output, thereby adjusting the driving ability to enhance data read and output operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If the size of transistors is increased to enhance driving ability, then the driving ability for data output is improved, but the circuit interval becomes narrower and the layout becomes more difficult
Solution Approach 1:
The page buffer is divided into multiple data buffering units (first data buffering unit and second data buffering units) that can be selectively activated. This segmentation allows the circuit to achieve high driving ability when needed while maintaining a compact layout when operating in a reduced mode, resolving the contradiction between transistor size and circuit interval.
Solution Approach 2:
The circuit configuration dynamically changes by selectively activating or deactivating current paths between the data buffering units based on operating conditions. The control block adjusts which units are active, allowing the driving ability to be adapted to different scenarios without requiring all units to be permanently configured at maximum size.
2Speed
If the size of transistors is increased to enhance driving ability, then the data read operation speed is improved, but the transistor size increase is limited by circuit interval constraints
Solution Approach 1:
Multiple data buffering units are combined to work together, where the first data buffering unit latches data and second data buffering units can be activated to form additional current paths. This merging of multiple units provides enhanced driving ability and faster read speeds without requiring any single transistor to be excessively large.
3Productivity
If multiple data buffering units are activated to increase driving ability, then the data output speed is improved, but the current path control becomes more complex
Solution Approach 1:
A control block is introduced as an intermediary component that manages the activation and deactivation of current paths between the data buffering units. This control block simplifies the complexity of managing multiple current paths by providing centralized control logic that determines when and how to activate additional buffering units based on data read operation requirements.
Data Source
AI summary
A semiconductor memory device includes a plurality of data buffering units corresponding to a data line, wherein the data buffering units include a first data buffering unit suitable for latching data stored in a memory cell in a data read operation, and second data buffering units, an output unit suitable for outputting the data latched in the first data buffering unit, and a control block suitable for controlling a current path to be formed between the second data buffering units and the output unit in the data read operation.