Nonvolatile Memory Discharge Circuit for Fast Terminal Reset
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Solution Overview
Problem
Existing nonvolatile semiconductor memory devices face challenges in efficiently discharging terminals after an erase operation, leading to longer discharge times and increased complexity and manufacturing costs due to the need for high withstand voltage elements and complex circuit designs.
Innovation Solution
A discharge circuit that includes a plurality of floating gate type MOS memory cell transistors with constant current transistors and switching transistors, which are turned on simultaneously to manage the discharge of terminals, reducing discharge time and preventing latchup by maintaining a stable constant current supply.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional discharge circuits are used with high withstand voltage elements, then reliability is improved, but device complexity and manufacturing costs increase
Solution Approach 1:
The patent changes the voltage parameter management by using constant current transistors to control discharge current rather than relying on high withstand voltage elements. The discharge transistor is turned on at a timing when the word line voltage is below a predetermined level, creating a voltage threshold parameter that simplifies the circuit requirements while maintaining reliable discharge operation.
Solution Approach 2:
The patent replaces expensive high withstand voltage elements with standard constant current transistors and switching transistors that are cheaper and more commonly available. The constant current transistor provides sufficient control for discharge operations without requiring the high voltage tolerance of specialized components, reducing manufacturing costs and device complexity.
2Reliability
If conventional discharge circuits are used, then discharge operation is achieved, but discharge time increases to about 500 ns
Solution Approach 1:
The patent applies preliminary action by pre-charging the bit line to a predetermined voltage level before the erase operation completes. This preliminary voltage preparation allows the discharge transistor to quickly clamp the bit line voltage when turned on, reducing the overall discharge time from 500 ns to approximately 200 ns without compromising discharge completeness.
Solution Approach 2:
The patent implements periodic control of the discharge transistor by turning it on at specific timing intervals - specifically when the word line voltage drops below a predetermined level during the erase operation. This periodic switching approach optimizes the discharge timing to achieve faster overall discharge performance while maintaining reliable operation.
3Ease of manufacture
If simple circuit designs are used, then manufacturing costs are reduced, but latchup conditions may occur
Solution Approach 1:
The patent implements feedback control by monitoring the word line voltage level and using this information to control the discharge transistor timing. The discharge transistor is turned on when the word line voltage falls below a predetermined threshold, creating a feedback mechanism that ensures discharge occurs at the optimal moment to prevent latchup while using standard, cost-effective components.
Solution Approach 2:
The constant current transistor serves as an intermediary element between the discharge transistor and the bit line. It provides controlled current limiting during discharge, preventing excessive current that could cause latchup conditions while allowing the use of simpler, lower-cost switching transistors instead of complex high-voltage protection circuits.
Data Source
AI summary
A discharge circuit for a floating gate type MOS memory cell transistor disposed in a memory array region of a nonvolatile semiconductor memory device, the memory cell region being formed in P-well, the P-well being formed in an N-well, and the N-well being formed in a P-type semiconductor substrate, includes a word line discharge circuit providing a word line control voltage and a bulk discharge circuit providing a voltage to the P-well during a discharge operation. Constant current transistors and switching transistors in the word line discharge circuit and the bulk discharge circuit are simultaneously turned ON during at least a portion of the discharge operation.