Column Redundancy Fuse Block Edge Placement for Die Area Optimization
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Solution Overview
Problem
The increasing defect density in semiconductor integrated circuits due to reduced chip size leads to lower product yield, and existing redundancy circuits, such as fuse blocks, occupy significant area due to laser alignment tolerance and layout limitations, hindering effective die integration and increasing the area of column control blocks.
Innovation Solution
A semiconductor integrated circuit design that positions the column redundancy fuse block at the edge area, allowing the fuse set array to be aligned without considering interconnection detours, thereby reducing the area occupied by the fuse set array and improving alignment efficiency, with the fuse blowing information block inputting signals through the memory cell array to the column control block.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the fuse set array is positioned in the column control block between banks, then column redundancy function is achieved, but the area of the column control block is enlarged and the effective net die area is reduced
Solution Approach 1:
The fuse set array is extracted from the column control block and repositioned to the edge area of the semiconductor chip. This separation removes the area-consuming fuse structures from the critical column control block region, thereby reducing the effective net die area while preserving the column redundancy function through the relocated fuse array.
Solution Approach 2:
The fuse set array is relocated from the internal column control block area to the peripheral edge area of the chip. This spatial repositioning utilizes the previously underutilized edge region, effectively redistributing functional elements to optimize the overall area utilization and increase the effective net die area.
2Ease of manufacture
If data input/output interconnections are configured to detour the upper portion of the fuse set, then laser blowing is enabled, but the layout of interconnections is limited and signal delay increases
Solution Approach 1:
The fuse set array is extracted from its position that required interconnection detours and relocated to the edge area. This removal eliminates the need for data input/output interconnections to detour around the fuse structures, allowing straight-line routing that reduces signal delay while maintaining laser blowing capability through the repositioned fuse array.
3Manufacturing precision
If the pitch between fuses is not reduced due to laser alignment tolerance, then laser blowing precision is maintained, but the area of the fuse set array is increased
Solution Approach 1:
The fuse set array is relocated to the edge area of the chip, utilizing the peripheral space that does not constrain the pitch between fuses. This positional change allows maintaining the required pitch for laser alignment tolerance while effectively using the available edge area, thereby preventing the fuse array from occupying critical central area and increasing the effective net die area.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This design reduces the area occupied by the column redundancy fuse block, enhances alignment efficiency, and increases the effective net die area by allowing straight-line data input/output interconnections, thereby improving power mesh characteristics and reducing crosstalk and signal delay.
Implementation Method 1
a program for each fuse set can be executed through a selective laser cutting (or blowing)
Data Source
AI summary
A semiconductor integrated circuit includes a column redundancy fuse block having a fuse set array having a plurality of fuse sets including a plurality of column address fuses, and a fuse blowing information block configured to output a fuse blowing determination signal of a corresponding column based on a cutting state of the column address fuses, wherein the column redundancy fuse is disposed in the edge area, wherein the fuse blowing determination signal is inputted to a column control block through upper portion of a memory cell array of a corresponding bank.