Non-volatile Memory Sub-block Erase Control via GIDL
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Solution Overview
Problem
Due to process variations during manufacturing, non-volatile memory systems experience different threshold voltage distributions across sub-blocks, leading to errors during programming and data retention issues, necessitating tight and uniform erased threshold voltage distributions.
Innovation Solution
Adjusting the magnitude of Gate Induced Drain Leakage (GIDL) separately for multiple sub-blocks in a non-volatile memory system using GIDL generation transistors to generate charge carriers, allowing for independent control of threshold voltage changes in memory cells.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of operation
If a single erase voltage is applied to the entire block, then the erase process is simple to control, but the threshold voltage distribution becomes non-uniform across sub-blocks due to process variations
Solution Approach 1:
The memory block is divided into multiple sub-blocks, each with independent control capability. The control circuit applies different erase voltages to different sub-blocks based on their specific threshold voltage distribution characteristics, allowing precise control of the erase process for each sub-block while maintaining overall system manageability
Solution Approach 2:
Different sub-blocks within the same block are treated with different erase voltages according to their local characteristics. The control circuit identifies sub-blocks with non-uniform threshold voltage distributions and applies adjusted erase voltages specifically to those sub-blocks, leaving other sub-blocks with uniform distributions unchanged
2Reliability
If the erase voltage is increased to ensure complete erasure, then data retention improves, but errors during programming increase due to excessive threshold voltage changes
Solution Approach 1:
The erase voltage parameter is dynamically adjusted based on the measured threshold voltage distribution of each sub-block. Sub-blocks requiring stronger erasure receive higher voltages, while sub-blocks already close to the target distribution receive lower voltages, optimizing the balance between complete erasure and preventing excessive threshold voltage shifts
3Ease of manufacture
If process variations are not compensated, then the manufacturing process remains simple, but programming errors and data retention issues occur
Solution Approach 1:
The control circuit measures the threshold voltage distribution of each sub-block and uses this feedback information to determine the appropriate erase voltage to apply. This closed-loop approach compensates for process variations automatically, ensuring programming accuracy without requiring complex manufacturing process control
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach ensures tight and uniform erased threshold voltage distributions, reducing errors and improving data retention by optimizing the erase process across sub-blocks.
Implementation Method 1
adjusting the magnitude of Gate Induced Drain Leakage (GIDL) separately for multiple sub-blocks in a non-volatile memory system using GIDL generation transistors to generate charge carriers
Data Source
AI summary
In order to achieve tight and uniform erased threshold voltage distributions in a non-volatile memory system that includes non-volatile memory cells arranged in blocks that have multiple sub-blocks and has an erase process using gate induced drain leakage (GIDL) to generate charge carriers that change threshold voltage of the memory cells, the magnitude of the GIDL is adjusted separately for the sub-blocks.