Conditional Valley Tracking for Memory Read Calibration
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Solution Overview
Problem
Existing memory sub-systems face challenges in accurately reading data due to cell-to-cell interference, which leads to widening of threshold voltage distributions and degradation of read window budget, resulting in increased errors and reduced memory device reliability.
Innovation Solution
Implementing conditional valley tracking during corrective reads, where the controller obtains cell state information for each group of adjacent cells and uses valley tracking to calibrate read level offsets for each bin of target cells, allowing for more accurate reading and improved reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If traditional reading methods are used, then the reading process is simple and fast, but cell-to-cell interference causes widening of threshold voltage distributions and degradation of read window budget, resulting in increased errors
Solution Approach 1:
The patent segments the reading process into multiple corrective read iterations, where each iteration reads a subset of memory cells and updates read levels based on observed errors. This segmentation allows the system to improve read accuracy by addressing cell-to-cell interference incrementally, rather than attempting to correct all errors in a single read operation.
Solution Approach 2:
The patent implements feedback by using the results of each corrective read to update the read levels for subsequent reads. The controller adjusts the read levels based on the threshold voltage distributions observed in previous reads, creating a closed-loop system that continuously improves read accuracy while managing the complexity of the reading process.
2Measurement precision
If corrective reads are performed to improve read accuracy, then errors are reduced, but the reading time and operational complexity increase
Solution Approach 1:
The patent applies partial action by performing corrective reads only on subsets of memory cells in each iteration rather than reading all cells every time. This approach achieves improved read level accuracy for critical cells while minimizing the overall time loss, as not all cells require the same level of correction in each reading cycle.
3Manufacturing precision
If multiple corrective reads are performed to calibrate read levels, then threshold voltage distribution accuracy improves, but the number of operations and energy consumption increase
Solution Approach 1:
The patent applies preliminary action by performing initial corrective reads to establish accurate read levels before normal reading operations. Once the read levels are calibrated through preliminary corrective reads, the system can perform standard reads with minimal energy consumption, as the costly corrective read operations are only needed periodically to maintain accuracy.
Data Source
AI summary
An example memory device includes a memory array and processing logic, operatively coupled with the memory array. The processing logic is configured to perform operations, including: identifying a set of sample voltages associated with a chosen read level; obtaining, for each sample voltage of the set of sample voltages, a cell count corresponding to a number of target cells of the memory array that have a threshold voltage lower than the sample voltage; and determining, based on the cell count, a calibrated read level associated with a state information bin to which the target cells are assigned.