NAND Flash Programming with Partial State Thresholds

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Solution Overview

Problem

Current high-performance program operations in solid-state storage, such as NAND flash memory, face challenges with resource allocation and peak power consumption, leading to prolonged operation times and potential voltage drops that can cause memory devices to malfunction, especially when multiple dies work in parallel.

Innovation Solution

A non-volatile storage controller identifies a threshold number of correctable bit flips and programs data in stages, initially programming to a partial state with fewer pulses, allowing for early resource release and reduced peak power consumption, with additional pulses applied later to ensure accurate programming.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If data is programmed to a full state with sufficient program pulses to ensure zero bit errors, then manufacturing precision is improved, but program operation time increases and productivity decreases

Engineering Contradiction:
Improveprogramming accuracyVSAvoidprogram operation speed
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The patent applies partial action by programming data to a partial state with sufficient pulses to correct only a threshold number of bit errors (e.g., 1-5 errors), rather than applying excessive pulses to achieve zero errors. This partial programming approach reduces program operation time while maintaining acceptable data integrity through error correction codes that can handle the remaining correctable errors.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The patent changes the parameter of programming pulses from a fixed high value designed to achieve zero errors to a variable value that adapts based on the desired error threshold. By adjusting the number and strength of program pulses to target a specific correctable error rate rather than zero errors, the system optimizes the balance between programming speed and data accuracy.

Inventive Principle:
Principle #35Parameter changes

2Productivity

If multiple memory dies work in parallel to improve productivity, then program operation speed increases, but peak power consumption increases causing voltage drops and reliability decreases

Engineering Contradiction:
Improveprogram operation speedVSAvoiddevice stability
Core Design Contradiction:
ProductivityVSReliability

Solution Approach 1:

By implementing partial programming that requires fewer program pulses to reach a correctable error state, the peak power consumption during parallel operations is reduced. This allows multiple memory dies to operate in parallel without causing excessive voltage drops, thereby maintaining system reliability while preserving the productivity benefits of parallel operation.

Inventive Principle:
Principle #16Partial or excessive action

3Manufacturing precision

If a high number of program pulses are applied to ensure accurate programming, then manufacturing precision is improved, but power consumption increases and duration of action increases

Engineering Contradiction:
Improveprogramming accuracyVSAvoidpower consumption
Core Design Contradiction:
Manufacturing precisionVSUse of energy by stationary object

Solution Approach 1:

The patent eliminates excessive action by determining the minimum number of program pulses required to achieve a acceptable error threshold rather than applying a high fixed number of pulses. This partial programming approach reduces power consumption while maintaining programming accuracy within correctable limits through error correction mechanisms.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The patent changes the programming parameter from a fixed high pulse count to a dynamic value that adapts to achieve a target error rate. By adjusting pulse parameters to match the actual requirements for correcting a threshold number of errors rather than forcing zero errors, power consumption is optimized without sacrificing essential programming accuracy.

Inventive Principle:
Principle #35Parameter changes

4Manufacturing precision

If resources are allocated to a single write operation until completion, then manufacturing precision is improved, but resources are not released and productivity decreases

Engineering Contradiction:
Improveprogramming accuracyVSAvoidresource utilization
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The patent implements partial programming where resources are allocated for a limited number of program pulses sufficient to reach a correctable error state, rather than holding resources until complete programming with zero errors is achieved. After this partial programming, resources can be released or reallocated to other operations, improving resource utilization while maintaining acceptable data integrity through error correction.

Inventive Principle:
Principle #16Partial or excessive action

Solution Approach 2:

The system performs preliminary programming action to reach a correctable error state, then releases resources for other operations. Error correction codes are applied to the partially programmed data to ensure integrity, allowing subsequent operations to proceed without waiting for complete programming of all data blocks.

Inventive Principle:
Principle #10Preliminary action

Data Source

PatentUS10482969B2Programming to a correctable amount of errors
Publication Date: 2019.11.19 SANDISK TECHNOLOGIES LLC
  • US10482969B2 patent drawing
  • US10482969B2 patent drawing
  • US10482969B2 patent drawing

AI summary

Apparatuses, systems, methods, and computer program products are disclosed for distributed program operation. One apparatus includes a non-volatile storage controller that identifies a threshold number of bit flips that can be corrected in an amount of read data and a memory die comprising a plurality of non-volatile memory cells. Here, the memory die receives the threshold number of bit flips from the non-volatile storage controller, programs data to a set of the non-volatile memory cells over a first number of program loop cycles, and programs the data to the set of non-volatile memory cells over an additional number of program loop cycles in response to the amount of bit flips in the set of memory cells exceeding the threshold number of bit flips.