Nonvolatile Memory Far Cell Programming Verification
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Solution Overview
Problem
Conventional NAND flash memory devices face performance limitations due to varying effective load capacitance along word lines, which affects the timing of program word line voltages, especially for memory cells located furthest from the row decoder circuit, impairing overall operational performance.
Innovation Solution
A nonvolatile memory device and method that adjust the duration of the program word line voltage application in successive program loops based on verification results, ensuring successful programming of memory cells, particularly the farthest cell from the row decoder, to optimize voltage timing and reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a fixed duration program voltage is applied to all memory cells, then the programming process is simple, but memory cells located furthest from the row decoder circuit fail to program successfully due to voltage timing issues
Solution Approach 1:
The patent segments the verification process into two distinct circuits: a first verification circuit that checks memory cells in a predetermined bit unit, and a second verification circuit that specifically checks the far cell (memory cell located furthest from the row decoder). This segmentation allows targeted verification of problematic cells without requiring complete re-verification of all cells, thus improving reliability while controlling complexity.
Solution Approach 2:
The patent performs preliminary verification of the far cell before finalizing the programming operation. By using the second verification circuit to check the far cell early in the process, the system can determine whether extended programming is needed before committing to additional programming cycles, preventing wasted operations and ensuring successful programming of distant cells.
2Reliability
If the program voltage application time is extended to ensure far cell programming, then all memory cells are reliably programmed, but the overall programming time increases
Solution Approach 1:
The patent applies partial action by verifying only the critical far cell and a predetermined bit unit rather than all memory cells. This selective verification approach uses minimal additional time to check the most problematic cells, allowing the system to extend programming duration only when necessary for far cells while avoiding unnecessary extensions for cells that are already successfully programmed.
Solution Approach 2:
The patent implements feedback mechanisms where the first and second verification circuits provide verification results back to the control logic. Based on these feedback results, the system dynamically adjusts whether to extend the program voltage application time in subsequent programming loops, ensuring far cell reliability while minimizing overall programming time by avoiding unnecessary extensions when far cells are already successfully programmed.
3Productivity
If conventional verification methods are used without far cell consideration, then the verification process is fast, but programming reliability for distant memory cells deteriorates
Solution Approach 1:
The patent applies local quality by creating specialized verification paths for different memory cell locations. The second verification circuit is specifically designed to check the far cell, which has different programming characteristics compared to other cells. This localized verification approach ensures that cells in critical positions receive appropriate verification attention without slowing down the verification of other cells, thus maintaining productivity while improving reliability.
Data Source
AI summary
In a nonvolatile memory device, a first verification result indicates whether a block of memory cells has been successfully programmed and a second verification result indicates whether a far cell in the block has been is successfully programmed. A controller defines the level and application time for the program voltage applied during a next program loop in response to the first and second verification results.