Stacked Resistive Memory Cell Array with Dynamic Mode Control
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Solution Overview
Problem
Current semiconductor memory devices face challenges in achieving high memory capacity, high operation speed, and low power consumption while maintaining data integrity without the need for refresh operations, particularly in resistive memory devices that require efficient programming modes to optimize chip size and performance.
Innovation Solution
A memory device with a stacked resistive memory cell array and a control circuit that identifies and accesses program modes for each memory cell layer, allowing for both single-level and multi-level cell modes based on address signals, enabling efficient data storage and retrieval by generating appropriate control signals and selecting the correct mode for each layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If resistive memory devices use stacked structures with multiple memory cell layers, then memory capacity and integration density are improved, but device complexity and manufacturing difficulty increase
Solution Approach 1:
The stacked resistive memory device is divided into multiple memory cell layers (first memory cell layer, second memory cell layer, etc.) stacked on the semiconductor substrate. Each layer can be independently controlled and accessed through separate word lines and bit lines, allowing the system to achieve high memory capacity through segmentation while maintaining manageable complexity through modular architecture.
Solution Approach 2:
The patent transitions from planar memory structures to a three-dimensional stacked architecture. By adding the vertical dimension with multiple stacked layers, the device achieves significantly higher integration density and memory capacity without proportionally increasing the chip footprint, thus improving capacity while controlling overall device complexity.
2Productivity
If resistive memory devices implement multiple programming modes (single-level and multi-level cell modes), then memory usage efficiency and storage density are improved, but control circuit complexity increases
Solution Approach 1:
The control circuit is designed to dynamically select between different programming modes (single-level cell mode and multi-level cell mode) based on the address signal and program information. This dynamic adaptability allows the system to optimize memory usage efficiency for different storage requirements while managing control complexity through conditional logic rather than fixed complex circuits.
Solution Approach 2:
The system changes operational parameters (programming modes) based on the memory cell layer being accessed. By adjusting the programming mode parameter according to the selected layer and storage requirements, the device achieves variable memory usage efficiency without requiring a completely different control circuit for each mode, thus improving productivity while controlling complexity.
3Quantity of substance
If resistive memory devices use multi-level cell modes for higher storage density, then data storage capacity per cell is improved, but reliability and data integrity may worsen
Solution Approach 1:
Different memory cell layers can be configured with different programming modes according to their specific requirements. Layers requiring higher storage density can use multi-level cell modes, while layers requiring higher reliability can use single-level cell modes. This local differentiation allows the system to optimize both storage density and data integrity simultaneously by applying appropriate quality characteristics to appropriate locations.
Data Source
AI summary
A memory device includes a stacked resistive memory cell array comprising a plurality of resistive memory cell layers stacked on a semiconductor substrate, wherein respective memory cell layers are configured to store data according to respective program modes comprising a number of bits per cell. The memory device further includes a control circuit configured to identify a program mode of a selected memory cell layer responsive to an address signal and to access the selected memory cell layer responsive to the address signal according to the identified program mode. The program modes may include a single-level cell mode and at least one multi-level cell mode.