Semiconductor Element Isolation Structure for Leak Current Reduction

Resolve Bottlenecks,
Find Innovative SolutionsGenerate Solutions

Solution Overview

Problem

Current semiconductor devices face reliability issues due to leak currents caused by incomplete isolation of field effect transistors, leading to reduced performance and efficiency.

Innovation Solution

The semiconductor device incorporates a recessed portion in the element isolation structure, with a protruding portion above the surface, surrounding the diffusion regions, to prevent semiconductor layer remnants and enhance isolation, thereby reducing leak currents.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If a conventional element isolation structure is used, then the manufacturing process is simple, but leak currents occur due to incomplete isolation of field effect transistors

Engineering Contradiction:

Improveisolation effectivenessVSAvoidelement isolation structure

Core Design Contradiction:

ReliabilityVSDevice complexity

Solution Approach 1:

The element isolation structure is segmented into multiple portions: a first portion embedded in the semiconductor layer and a second portion positioned between the diffusion region and the first region. This segmentation allows each portion to perform specific isolation functions, effectively preventing leak currents while maintaining manufacturing feasibility through standardized processing steps.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The element isolation structure extends in the vertical dimension with the second portion protruding above the semiconductor layer surface. This dimensional extension creates additional isolation space that prevents leak currents without increasing lateral footprint, resolving the contradiction between isolation effectiveness and device area constraints.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Reliability

If the element isolation is embedded deep in the semiconductor layer, then isolation effectiveness improves, but manufacturing precision requirements increase

Engineering Contradiction:

Improveisolation completenessVSAvoidisolation structure alignment

Core Design Contradiction:

ReliabilityVSManufacturing precision

Solution Approach 1:

The first portion of the element isolation is formed embedded in the semiconductor layer before the diffusion regions are created. This preliminary action establishes a stable isolation foundation that guides subsequent processing steps, reducing alignment precision requirements for later stages while ensuring complete isolation effectiveness.

Inventive Principle:

Principle #10Preliminary action

Data Source

PatentUS12120870B2Semiconductor device and method for manufacturing semiconductor device

Publication Date: 2024.10.15 KIOXIA CORP

AI summary

According to one embodiment, a semiconductor device includes a first region including a memory cell and a second region including a peripheral circuit. The second region includes a diffusion region provided on a surface of the semiconductor layer, a gate insulating film provided on the diffusion region, a gate electrode provided on the gate insulating film, an insulator layer provided on the diffusion region and surrounding the gate electrode, and an element isolation that is embedded in the semiconductor layer and surrounds the diffusion region. The element isolation includes a first region that is recessed below the surface of the diffusion region and a second region that is between the diffusion region and the first region and includes a protrusion protruding to a level higher than the first region.