Semiconductor Error Check Scrub Circuit for High-Speed Data Reliability
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Solution Overview
Problem
As semiconductor devices operate at faster speeds, the probability of data transmission errors increases, necessitating advanced error correction mechanisms to ensure reliable data transmission, but existing solutions are inadequate in managing these errors effectively.
Innovation Solution
The implementation of an error check and scrub (ECS) system within semiconductor devices, which includes an ECS command generation circuit and an ECS control circuit to perform ECS operations, such as generating ECS mode signals, active commands, read commands, and write commands, to detect and correct errors, and an error log storage circuit to track and manage error data.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If data transmission speed is increased to improve operation speed, then productivity is improved, but the probability of data transmission errors increases, worsening reliability
Solution Approach 1:
The patent applies preliminary action by generating error check codes (ECC/EDC) before data transmission occurs. The encoding circuit prepares correction codes in advance, and the system performs error checking and scrubbing operations proactively during idle periods or before potential errors occur, rather than reacting after errors happen. This allows high-speed transmission while maintaining reliability through pre-configured error protection mechanisms.
2Reliability
If error correction mechanisms are added to improve reliability, then reliability is improved, but device complexity increases
Solution Approach 1:
The patent merges error correction functionality with existing memory control structures. The error check code generation is integrated into the memory controller, and the same control circuits that manage normal memory operations are used to coordinate ECS operations. The error correction code and error detection code systems are combined into a unified error management framework, reducing the need for separate dedicated complexity while maintaining reliability.
Solution Approach 2:
The patent implements multi-functionality by designing the error correction system to handle multiple error types (correctable and uncorrectable errors) and multiple operation modes (encoding, decoding, error checking, scrubbing) using a unified set of circuits. The same control logic manages both ECC and EDC operations, and the system can adaptively switch between different error correction strategies based on the situation, reducing overall system complexity through versatile design.
3Reliability
If error checking operations are performed continuously to improve reliability, then reliability is improved, but power consumption increases
Solution Approach 1:
The patent implements periodic action by performing error checking and scrubbing operations at scheduled intervals rather than continuously. The system uses refresh commands and idle signals to trigger ECS operations periodically, and the error log storage circuit maintains error information between checking cycles. This periodic approach ensures reliability through regular error detection while significantly reducing power consumption compared to continuous monitoring.
Data Source
AI summary
A semiconductor device includes an error check and scrub (ECS) command generation circuit and an ECS control circuit. The ECS command generation circuit generates an internal refresh command after generating an ECS command based on a refresh command and an idle signal. The ECS control circuit generates an ECS mode signal that is activated during an ECS operation based on the ECS command. The ECS control circuit also generates an ECS active command, an ECS read command, and an ECS write command for performing the ECS operation based on the ECS command.