NVM Cell Reading Circuit for Overlapping Threshold Voltage States

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Solution Overview

Problem

Non-volatile memory (NVM) cells, particularly multi-level cells, face challenges in accurately reading logical states due to threshold voltage fluctuations and drift, leading to overlapping voltage distributions that result in data corruption.

Innovation Solution

A threshold voltage detection circuit and decoder circuit system that uses a multifactor function to account for approximate threshold voltages from adjacent charge storage regions, allowing for accurate decoding of logical states even when distributions overlap.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Loss of information

If multi-level NVM cells are used to increase storage capacity, then the quantity of information stored per cell increases, but threshold voltage distributions overlap causing data corruption

Engineering Contradiction:
Improvedata accuracyVSAvoidreading accuracy
Core Design Contradiction:
Loss of informationVSReliability

Solution Approach 1:

The patent implements a feedback mechanism where the read operation itself modifies the threshold voltage of the NVM cell. By applying a read voltage that induces a controlled shift in threshold voltage, the system creates a feedback effect that separates overlapping voltage distributions. This feedback-based approach allows the system to compensate for the overlap problem inherent in multi-level cells, enabling accurate data retrieval while maintaining high storage capacity.

Inventive Principle:
Principle #23Feedback

2Productivity

If threshold voltage detection is performed to read logical states, then data can be retrieved from NVM cells, but overlapping voltage distributions cause misinterpretation of logical states

Engineering Contradiction:
Improvedata retrieval speedVSAvoidthreshold voltage measurement accuracy
Core Design Contradiction:
ProductivityVSMeasurement precision

Solution Approach 1:

The patent introduces an intermediary mechanism in the form of a controlled threshold voltage shift during the read operation. Rather than directly measuring the original threshold voltage, the system uses the shifted voltage as an intermediary indicator. This intermediary approach allows the system to distinguish between overlapping logical states by measuring the magnitude and direction of the voltage shift, thereby maintaining both fast retrieval and high measurement precision.

Inventive Principle:
Principle #24Intermediary (Mediator)

3Device complexity

If conventional reading methods are used for NVM cells, then the device complexity remains low, but data corruption occurs due to overlapping voltage distributions

Engineering Contradiction:
Improvereading circuit complexityVSAvoiddata integrity
Core Design Contradiction:
Device complexityVSLoss of information

Solution Approach 1:

The patent changes the operational parameters of the NVM cell during the read operation. Specifically, it modifies the voltage applied to the cell to induce a controlled threshold voltage shift. This parameter change transforms the read operation from a simple voltage measurement into a dynamic process where the system actively manipulates the cell's electrical characteristics. The modified parameter approach enables accurate data retrieval without requiring complex additional circuitry, maintaining simplicity while ensuring data integrity.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS8264884B2Methods, circuits and systems for reading non-volatile memory cells
Publication Date: 2012.09.11 SPANSION ISRAEL LTD
  • US8264884B2 patent drawing
  • US8264884B2 patent drawing
  • US8264884B2 patent drawing

AI summary

The present invention includes methods, circuits and systems for reading non-volatile memory (“NVM”) cells, including multi-level NVM cells. According to some embodiments of the present invention, there may be provided a NVM cell threshold voltage detection circuit adapted to detect an approximate threshold voltage associated with a charge storage region of a NVM cell, where the NVM cell may be a single or a multi-charge storage region cell. A decoder circuit may be adapted to decode and/or indicate the logical state of a NVM cell charge storage region by mapping or converting a detected approximate threshold voltage of the charge storage region into a logical state value.