Binary Neural Network Inference in NAND Memory Arrays
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Solution Overview
Problem
Artificial neural networks are computationally intensive and require significant data transfer for weight loading and processing, which is energy inefficient and limits their scalability in machine learning applications.
Innovation Solution
The use of Binary Neural Networks (BNNs) with binary weights and inputs stored in NAND memory arrays, where each weight is represented by a pair of series-connected memory cells and inputs are applied as voltage patterns to perform in-array multiplication, reducing computational complexity and memory requirements.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If traditional artificial neural networks are used with full precision weights and inputs, then high computational accuracy is achieved, but energy consumption and data transfer requirements increase significantly
Solution Approach 1:
The patent applies parameter changes by quantizing weights and inputs from full precision (32-bit floating point) to binary values (-1, +1), fundamentally changing the precision parameter to reduce computational complexity and energy consumption while maintaining acceptable accuracy through the in-memory computing approach
Solution Approach 2:
The patent replaces traditional mechanical computing operations (multiplication and accumulation in separate processing units) with electrical phenomena occurring naturally in the memory array during read operations, where current flow through memory cells directly performs the multiply-accumulate operation, eliminating the need for separate processing hardware
2Adaptability or versatility
If traditional neural network processing is used with separate memory and processing units, then computational flexibility is maintained, but data transfer between memory and processing units creates bottlenecks
Solution Approach 1:
The patent merges the memory array and processing functions into a single integrated system where the NAND memory array performs both data storage and computational operations simultaneously, eliminating the data transfer bottleneck between separate memory and processing units while maintaining computational flexibility through programmable weight configurations
Solution Approach 2:
The patent makes the memory array universal by enabling it to perform multiple functions: storing weights, performing multiply-accumulate operations, and supporting different neural network configurations, thereby eliminating the need for dedicated processing units while maintaining adaptability
3Loss of energy
If binary neural networks are implemented in NAND memory arrays, then energy dissipation and data movement are reduced, but manufacturing complexity and precision requirements increase
Solution Approach 1:
The patent uses standard, widely-manufactured NAND memory cells (which are inexpensive and well-understood) rather than requiring new, precision-critical memory structures, thereby reducing manufacturing precision requirements while achieving energy-efficient binary neural network computation through clever use of existing technology
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach significantly reduces energy dissipation and data movement by performing matrix multiplication within the memory array, enhancing the efficiency and scalability of neural network inference processes.
Implementation Method 1
an array of non-volatile memory cells arranged as NAND strings and configured to store a plurality of weights of a neural network
Implementation Method 2
The one or more control circuits are configured to receive a plurality of inputs for a layer of a neural network, convert the plurality of inputs into a corresponding plurality of voltage patterns, apply the plurality of voltage patterns to the array of non-volatile memory cells to thereby perform an in-array multiplication
Data Source
AI summary
Use of a NAND array architecture to realize a binary neural network (BNN) allows for matrix multiplication and accumulation to be performed within the memory array. A unit synapse for storing a weight of a BNN is stored in a pair of series connected memory cells. A binary input is applied as a pattern of voltage values on a pair of word lines connected to the unit synapse to perform the multiplication of the input with the weight by determining whether or not the unit synapse conducts. The results of such multiplications are determined by a sense amplifier, with the results accumulated by a counter.