Charge-Trapping Memory Disturb Leveling Circuit
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Solution Overview
Problem
Charge-trapping memory devices, such as NROM, face data invalidation due to disturbances from accessing one memory cell affecting neighboring cells, leading to bit failures that cannot be corrected by error correction codes, especially when the number of faulty bits exceeds two per segment, posing a risk to data consistency and application errors.
Innovation Solution
A charge-trapping memory device with a disturb detection circuit to monitor disturbances and a disturb leveling circuit that backups the programming state of memory cells if the disturbance level exceeds a predefined threshold, reducing bit errors by copying data to a safe location before non-correctable failures occur, and recycling memory cells to maintain storage capacity and extend lifespan.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If memory cells are accessed frequently for programming and erasing operations, then the memory device can be used extensively, but bit failures occur in neighboring memory cells due to disturbance, leading to data invalidation
Solution Approach 1:
The patent applies preliminary action by performing disturb leveling operations before bit failures become non-correctable. The controller proactively monitors disturbance levels in memory sectors and executes leveling operations (such as reprogramming or erasing) when disturbance thresholds are reached, preventing future data invalidation rather than reacting after failures occur
Solution Approach 2:
The patent implements feedback through the controller's monitoring of disturbance levels in memory sectors. The system continuously tracks the number of programming and erasing operations performed on each sector and uses this information to determine when disturb leveling operations are needed, creating a closed-loop control system that adapts to actual usage patterns
2Reliability
If error correction codes are used to correct bit failures, then data integrity can be maintained for single and double bit failures, but segments with more than two faulty bits cannot be corrected, posing a risk for application errors
Solution Approach 1:
The patent prevents the situation where more than two bit failures occur in a segment by performing disturb leveling operations proactively. By monitoring disturbance levels and executing leveling before cumulative disturbances cause multiple failures, the system ensures that ECC can continue to correct errors effectively without being overwhelmed by uncorrectable failure patterns
3Reliability
If disturb leveling operations are performed frequently to prevent bit failures, then data integrity is maintained, but additional programming operations increase wear on the memory device
Solution Approach 1:
The patent applies partial action by performing disturb leveling operations selectively rather than continuously. The controller monitors disturbance levels and only executes leveling operations when specific thresholds are reached, performing the minimum necessary actions to maintain data integrity without subjecting the memory device to excessive additional programming cycles
Solution Approach 2:
The patent changes the operational parameters of the memory device dynamically by adjusting when disturb leveling operations are performed based on monitored disturbance levels. The system adapts the frequency and timing of leveling operations according to actual usage patterns and disturbance accumulation, optimizing the balance between data integrity and device lifespan
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Prevents data loss by safely reading and preserving programming states, reducing bit errors, and extending the lifespan of the memory device by detecting and mitigating disturbances, ensuring data integrity and consistency even with multiple bit failures.
Implementation Method 1
a programming state of a memory cell of the device is stored by means of trapping electrons in a nitride layer placed between a control gate and a source/drain channel
Data Source
AI summary
A method for leveling bit errors in a charge-trapping memory device is included. The memory device has a first and a second sector of memory cells. The first sector is validated by counting a number of bit failures occurring in memory cells of the first sector, the bit failures caused by accessing memory cells of the second sector. Data stored in the first sector is backed up if the validating indicates a likelihood of a forthcoming failure in the first sector.