Hierarchical Defect Address Storage for Semiconductor Memory Repair

The patent divides the storage structure into a hierarchical system with a small-capacity buffer and a large-capacity memory device. The buffer stores essential defect information during testing, while the memory device stores the complete defective bit map. This segmentation allows the system to maintain high repair rates without requiring a large buffer, thus resolving the contradiction between storage capacity and area.

The patent introduces an intermediary structure (the memory device) that acts as an extension of the buffer. The buffer and memory device work together, with the buffer providing fast access during testing and the memory device providing large-capacity storage. This intermediary approach enables the system to achieve both high repair rates and reduced buffer area.

The patent performs preliminary defect identification and information storage during the test process itself. The small-capacity buffer continuously stores defect information as tests progress, enabling early detection and classification of defects. This preliminary action reduces the time required for subsequent analysis while maintaining complete defect identification accuracy.

The patent maintains continuous defect information storage throughout the test process rather than performing a single batch analysis after testing completes. The buffer continuously records defect data, allowing for real-time monitoring and faster subsequent processing. This continuous action reduces overall analysis time while ensuring all defects are captured.

The patent transitions from a single-dimension storage approach (buffer only or memory only) to a two-dimension hierarchical storage system. The buffer provides fast access for active testing, while the memory device provides extensive storage capacity. This dimensional change in the storage architecture enables the system to achieve both small buffer area and high repair rates simultaneously.

The patent implements a nested storage structure where the small-capacity buffer is embedded within a larger memory device context. The buffer handles immediate testing requirements while the memory device contains the complete defective bit map. This nesting allows the system to leverage both the speed of small storage and the capacity of large storage without requiring the full buffer area that a flat architecture would demand.