Semiconductor Memory Dual Address Register Random Access
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Solution Overview
Problem
Conventional cache read operations in NAND flash memory systems are limited to reading consecutive pages within a single block, preventing random access and slowing down data read operations when user data and management data are scattered across multiple blocks, which decreases data transfer rates.
Innovation Solution
A semiconductor memory device with a first and second address register system that allows reading a page and simultaneously transferring the address to the second register, enabling random access to arbitrary pages across multiple blocks, thereby speeding up data read operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional cache read operation is used to read consecutive pages within a single block, then reading speed within a block is improved, but random access capability is lost and data transfer rate decreases when data are scattered across multiple blocks
Solution Approach 1:
The patent divides the address register into two separate registers: a first address register for holding the current page address and a second address register for holding the next target page address. This segmentation allows the system to maintain the sequential reading capability within a block while simultaneously preparing for random access to pages in other blocks, thus resolving the contradiction between reading speed and random access capability.
Solution Approach 2:
The patent implements preliminary action by allowing the second address register to be loaded with the next target page address while the first address register is still being used for the current read operation. This advance preparation enables the system to switch to random access mode without waiting for the current read operation to complete, thereby maintaining high reading speed while enabling random access capability.
2Adaptability or versatility
If conventional read operation is performed on specific pages in each block, then random access to scattered data is enabled, but data transfer rate decreases due to sequential processing requirement
Solution Approach 1:
The patent ensures continuity of useful action by enabling overlapping operations: while data from the current page is being read and transferred, the next page address is already loaded into the second address register. This continuous preparation eliminates idle time between read operations, maintaining high data transfer rate even when accessing scattered data across multiple blocks.
Solution Approach 2:
The patent uses preliminary action by pre-loading the next target page address into the second address register during the current read operation. This advance preparation allows the system to immediately switch to the next page without address setup delay, thereby maintaining high productivity while enabling random access to scattered data.
3Device complexity
If single address register system is used, then device complexity is reduced, but ability to perform concurrent address operations is limited
Solution Approach 1:
The patent segments the address register into two independent registers (first and second address registers), each capable of holding and processing addresses independently. This segmentation enables concurrent address operations where one register can be updated while the other is being used for read operations, thereby increasing automation capability while maintaining relatively simple device complexity.
Solution Approach 2:
The patent makes the address register system multi-functional by having two address registers that can operate independently. The first address register handles current read operations while the second address register prepares for next operations, allowing the system to perform multiple address-related functions simultaneously without significantly increasing overall system complexity.
Data Source
AI summary
A semiconductor memory device includes a first memory cell array having a first plane which is composed of a plurality of blocks each having a plurality of memory cells, a sense circuit which reads data the memory cells, a sequencer which receives control signals from outside, a first address register, and a second address register which receives an output address from the first address register and outputs an address signal in response to an address control signal from the sequencer. In reading from the memory cells, the sequencer reads a page n in accordance with the address stored in the second address register, then transfers an address stored in the first address register to the second address register concurrently with outputting data read from the page n to outside and reads data from an arbitrary page m in accordance with the address transferred to the second address register.