Memory Device Concurrent Read Write Reconfiguration
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Solution Overview
Problem
Conventional non-volatile memory (NVM) devices, such as flash memory, face limitations in write operation speed and inability to perform read operations concurrently with write operations, which restricts their usage in systems that require direct execution of instructions from the memory device.
Innovation Solution
The implementation of a memory device that can automatically detect read operations during write operations and reconfigure the write process to minimize electrical noise and power consumption, allowing concurrent read and write operations by pausing, slowing down, or altering the write routine, ensuring accurate read execution without substantial adjustments to the read operation timing.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If write operations are performed in conventional NVM devices, then data is stored, but the write operation speed is slow and read operations cannot be performed concurrently
Solution Approach 1:
The memory array is divided into multiple independent blocks that can be accessed simultaneously. Write operations are performed on one block while read operations are performed on another block, enabling concurrent access without interference. This segmentation allows the system to overcome the limitation of sequential operations.
Solution Approach 2:
The system dynamically switches between different operational modes based on the current state. When a write operation is detected, the system can pause or slow down the write routine temporarily to allow read operations to proceed, then resume the write operation. This dynamic adjustment enables flexible concurrent operation management.
2Productivity
If write operations are performed at full speed, then write efficiency is maximized, but electrical noise increases and interferes with read operations
Solution Approach 1:
The write operation is performed in periodic pulses rather than continuous operation. During the intervals between write pulses, the system can perform read operations without significant noise interference. This periodic approach allows the write operation to maintain high overall speed while providing noise-free windows for read operations.
Solution Approach 2:
The write operation speed is dynamically adjusted based on the operational context. When read operations are needed, the write speed is reduced or paused temporarily. When only write operations are required, the system operates at full speed. This dynamic speed adjustment optimizes both productivity and noise reduction.
3Adaptability or versatility
If read operations are performed during write operations, then system flexibility is improved, but read accuracy may be compromised due to noise and power consumption
Solution Approach 1:
The memory system is divided into separate blocks that can be independently accessed. Read operations are performed on one block while write operations occur on another block, eliminating noise interference and ensuring read accuracy. This physical segmentation provides both concurrency and reliability.
Solution Approach 2:
The system detects write operations in advance and proactively adjusts the write routine to create a noise-free environment for subsequent read operations. By preparing the system state beforehand, read accuracy is ensured while still allowing concurrent operations to proceed.
Data Source
AI summary
A method of controlling a memory device can include: receiving, by an interface, a write command from a host; beginning execution of a write operation on a first array plane of a memory array in response to the write command, where the memory array includes a plurality of memory cells arranged in a plurality of array planes; receiving, by the interface, a read command from the host; reconfiguring the write operation in response to detection of the read command during execution of the write operation; beginning execution of a read operation on a second array plane in response to the read command; and restoring the configuration of the write operation after the read operation has at least partially been executed.