Memory Device Erase Control Transistor Threshold Voltage Management
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Solution Overview
Problem
The reliability of flash memory devices is compromised due to variations in threshold voltages of cell transistors, leading to decreased operational performance.
Innovation Solution
An operation method for a memory device that includes a sequence of erase and program operations on ground selection and erase control transistors, with specific voltage applications and verify steps to maintain optimal threshold voltage distributions, enhancing the reliability of the memory device.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional erase and program operations are performed on cell transistors, then data storage is achieved, but threshold voltage variations cause reliability degradation
Solution Approach 1:
The memory block is divided into multiple segments including cell transistors, ground selection transistors, and erase control transistors. The erase control transistors are positioned between the ground selection transistors and the substrate, creating distinct functional zones that can be independently controlled during erase and program operations, thereby improving threshold voltage uniformity and reliability
Solution Approach 2:
Erase control transistors are used to perform preliminary erase operations on the ground selection transistors before program operations are executed. This preliminary action ensures that the ground selection transistors start from a known threshold voltage state, preventing unintended programming and maintaining reliable operation throughout the device
2Reliability
If ground selection transistors are programmed without proper control, then data writing is achieved, but unintended programming and leakage occur due to threshold voltage drift
Solution Approach 1:
Erase control transistors serve as intermediary elements between the substrate and ground selection transistors. These intermediaries regulate the erase operations affecting ground selection transistors, ensuring that threshold voltages remain within desired ranges and preventing harmful effects such as unintended programming and leakage currents
Solution Approach 2:
The device employs verify operations after program and erase cycles to monitor threshold voltage states of ground selection transistors. Based on these verification results, additional program or erase operations can be performed to ensure threshold voltages remain within specified ranges, creating a feedback control mechanism that prevents operational failures
Data Source
AI summary
Disclosed is an operation method of a memory device that includes a memory block including a plurality of cell transistors stacked in a direction perpendicular to a substrate. The plurality of cell transistors may include a ground selection transistor and an erase control transistor. The erase control transistor may be between the substrate and the ground selection transistor. The operation method may include performing a first erase operation on the ground selection transistor, performing a first program operation on the erase control transistor after the first erase operation, performing a second program operation on the ground selection transistor after the first program operation, and performing a second erase operation on the erase control transistor after the second program operation.