Semiconductor Device Programming Voltage Control
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Solution Overview
Problem
Current semiconductor memory devices, particularly non-volatile NAND flash memories, face challenges in optimizing programming efficiency and reducing programming time due to limitations in voltage differences and bit line voltage management during programming operations.
Innovation Solution
The proposed solution involves a method of operating semiconductor devices that includes performing multiple program operations with varying voltage differences between pre-verify and main verify voltages, and adjusting bit line voltages accordingly, allowing for a more efficient distribution of threshold voltages and reduced programming time by incrementing bit line voltages based on the level differences between these voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a fixed voltage difference between pre-verify and main verify voltages is used, then the programming operation is simple, but the programming time cannot be reduced and distribution efficiency is limited
Solution Approach 1:
The patent applies dynamics by making the voltage difference between pre-verify and main verify voltages variable rather than fixed. The control logic dynamically adjusts this voltage difference based on the programming state, transitioning from a larger difference in early stages to a smaller difference in later stages, thereby optimizing programming speed at different phases without requiring complex manual intervention
Solution Approach 2:
The patent implements parameter changes by systematically varying the voltage difference parameter between pre-verify and main verify voltages throughout the programming operation. This parameter adjustment allows the system to adapt the verification threshold dynamically, improving programming efficiency by reducing unnecessary iterations while maintaining accurate threshold voltage distribution control
2Loss of time
If the bit line voltage is kept constant during programming, then the control is simple, but the programming time cannot be reduced
Solution Approach 1:
The patent applies periodic action through the repeated verification cycles that alternate between pre-verify and main verify operations. Each cycle periodically checks the programming status and adjusts voltages accordingly, creating a rhythmic verification pattern that efficiently converges on the target threshold voltage while minimizing unnecessary programming iterations
Solution Approach 2:
The patent implements feedback by continuously monitoring the programming status through verification operations and using this information to adjust the bit line voltage and voltage difference parameters. The control logic receives feedback from the verification results and modifies the programming parameters accordingly, creating a closed-loop system that optimizes programming time based on actual progress
3Manufacturing precision
If a large voltage difference between pre-verify and main verify voltages is used, then the verification is strict, but the distribution efficiency and programming speed are reduced
Solution Approach 1:
The patent applies dynamics by transitioning the voltage difference from large to small based on programming progress. In early stages, a larger voltage difference provides strict verification for accurate threshold voltage distribution. As programming approaches completion, the system dynamically reduces the voltage difference to speed up verification and reduce programming time, optimizing both precision and productivity at different phases
Data Source
AI summary
Provided herein may be a semiconductor device and a method of operating a semiconductor device. The method may include: performing a first program operation on a selected memory cell using a first program pulse, a first bit line voltage, a first pre-verify voltage, and a first main verify voltage, with a first level difference between the first pre-verify voltage and the first main verify voltage; and performing a second program operation on the selected memory cell using a second program pulse, a second bit line voltage, a second pre-verify voltage, and a second main verify voltage, with a second level difference between the second pre-verify voltage and the second main verify voltage. The second level difference may be less than the first level difference, and the second bit line voltage may have a level higher than a level of the first bit line voltage.