3D Memory Semiconductor Layer Layout for Easier Lead Formation
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
As semiconductor manufacturing processes advance with smaller feature sizes and increased memory density, ensuring uniform depths of channel holes in three-dimensional memory devices becomes challenging, leading to varying heights of initial channel structures and limitations in lead process complexity and material selection.
Innovation Solution
A semiconductor device and fabrication method featuring a stack structure with non-overlapping projections of the semiconductor layer and channel structures, allowing for a thinner insulating layer and reduced aspect ratio of leading-out portions, enabling the use of aluminum and omitting tungsten filling processes, thus simplifying the lead process and expanding material options.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the number of stack layers is increased to improve memory capacity, then memory density is improved, but channel hole depth uniformity deteriorates
Solution Approach 1:
The patent transitions from a two-dimensional planar memory structure to a three-dimensional vertical stack structure. By stacking multiple memory layers vertically, the patent achieves higher memory capacity without increasing the footprint area. The stack structure includes alternating layers of semiconductor material and insulating material, creating vertical channels that extend through multiple layers, thereby solving the contradiction between memory capacity and manufacturing precision by utilizing the third dimension.
Solution Approach 2:
The patent implements a nested structure where channel structures are formed within the stack layers. The channel structures extend vertically through multiple stacked layers, with each layer containing nested functional components. This nesting approach allows multiple memory cells to be packed within a compact vertical structure, improving memory density while maintaining controllable channel dimensions through precise layer thickness control.
2Manufacturing precision
If channel hole depth uniformity is difficult to ensure, then initial channel structure height varies, but formation location of leading-out components is limited, increasing lead process difficulty
Solution Approach 1:
The patent performs preliminary planarization by forming an insulating layer over the stack structure before creating the leading-out portions. This preliminary action creates a flat surface that compensates for any variations in channel structure heights. By establishing this planar reference surface in advance, the patent enables subsequent lead formation processes to proceed without being affected by underlying height variations, thereby reducing lead process difficulty.
Solution Approach 2:
The patent introduces an insulating layer as an intermediary between the stack structure and the leading-out portions. This intermediary layer serves as a buffer that decouples the height variations of the channel structures from the lead formation process. The insulating layer provides a uniform surface for lead formation while isolating the leads from direct contact with the varying channel structure tops, thus facilitating easier manufacturing.
3Manufacturing precision
If a thicker insulating layer is used to cover variations, then leading-out portion aspect ratio increases, but material selection and process options are limited
Solution Approach 1:
The patent optimizes the thickness parameter of the insulating layer to achieve the right balance between surface planarity and aspect ratio. Rather than using an excessively thick insulating layer, the patent carefully controls the layer thickness to provide sufficient planarization while maintaining acceptable aspect ratios for the leading-out portions. This parameter optimization enables the use of conventional filling materials and processes.
Solution Approach 2:
The patent applies the insulating layer with locally optimized properties. The insulating material is selected and deposited with specific characteristics that provide adequate planarization for the lead formation areas while maintaining appropriate thickness to avoid excessive aspect ratios. The local quality of the insulating layer is tailored to meet the specific requirements of the leading-out portion formation process.
Data Source
AI summary
Aspect of the disclosure provide a semiconductor device including a stack structure having a core region in which a plurality of channel structures are formed, and a semiconductor layer located on one side of the stack structure in a stacking direction of the stack structure, the channel structures extending to the semiconductor layer, and projections of the semiconductor layer and the channel structures in a plane parallel to the stacking direction not overlapping. The semiconductor device can further include a first insulating layer at least located on a first surface of the semiconductor layer far away from the stack structure, and a first leading-out portion penetrating through a portion of the first insulating layer corresponding to the core region in the stacking direction and being in contact with the semiconductor layer.