3D Memory Cell Line Stack Layout for Lower Parasitic Capacitance
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Solution Overview
Problem
The challenge of increasing memory cell density and reducing parasitic capacitance in semiconductor devices is hindered by structural limitations, making it difficult to miniaturize memory cells effectively.
Innovation Solution
A semiconductor device design featuring a conductive line stack with double conductive lines stacked perpendicular to the substrate, laterally oriented conductive pads, and contact plugs connecting edge portions of these lines, along with a word line stack and capacitors coupled to active layers, enhances integration and reduces parasitic capacitance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the size of the memory cell is reduced to increase net die, then memory cell density increases, but parasitic capacitance increases and capacitance decreases
Solution Approach 1:
The patent transitions from planar two-dimensional memory cell arrangement to three-dimensional vertical stacking of memory cells. Multiple memory cells are stacked along the vertical direction (first direction) using through-silicon vias (TSVs) and interlayer dielectric structures, enabling higher memory cell density without increasing parasitic capacitance in the lateral plane.
Solution Approach 2:
The memory cell structure is divided into multiple stacked layers separated by interlayer dielectric layers. Each memory cell layer is independently structured with conductive lines, active regions, and capacitors, allowing parasitic capacitance to be managed at each layer rather than accumulating across a large planar area.
2Quantity of substance
If three-dimensional memory cells are implemented, then memory cell density increases, but structural complexity increases
Solution Approach 1:
The patent employs universal repeating structures for the interlayer dielectric layers and through-silicon via formations that can be applied across multiple memory cell layers. The same fabrication processes and material layers are reused in each stacked memory cell, reducing overall structural complexity despite the three-dimensional arrangement.
Solution Approach 2:
Multiple memory cells are nested vertically within a compact footprint area. Each memory cell is contained within a silicon substrate layer, with TSVs providing vertical interconnections through the substrate. This nesting approach achieves high density while maintaining a regular, manageable structural pattern.
Data Source
AI summary
A semiconductor device includes: a conductive line stack including a plurality of double conductive lines stacked over a substrate in a direction perpendicular to a surface of the substrate; conductive line pads laterally oriented between edge portions of each of the double conductive lines; and a contact plug contacting the edge portions of the double conductive lines.