3D Memory Cell Architecture with Longitudinal Spacers
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current 3D resistive memory architectures face challenges in increasing memory cell density, electrostatic control of transistors, and high manufacturing costs, with limited improvements in integration density and inefficient current intensity.
Innovation Solution
A 3D microelectronic device architecture featuring selection transistors with a channel wire structure, surrounded by a gate extending in the all-around configuration, and utilizing longitudinal spacers to cover source and drain regions, allowing for increased density and improved electrostatic control, along with a manufacturing method that reduces costs by using alternating semiconductor and dielectric layers without layer transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are stacked in 3D to increase density, then integration density is improved, but manufacturing complexity and cost increase
Solution Approach 1:
The patent transitions from planar 2D memory cell arrangement to vertical 3D stacking, where multiple memory cells are arranged along the vertical direction (z-axis) above a common transistor. This dimensional change enables increased storage density without proportionally increasing manufacturing complexity, as the stacked cells share common transistors and wiring structures.
Solution Approach 2:
The patent implements a shared transistor structure where a single transistor controls multiple stacked memory cells through selective wordline activation. This multi-functional approach allows one transistor to serve multiple memory cells, reducing the overall number of transistors needed and simplifying the manufacturing process compared to having dedicated transistors for each cell.
2Quantity of substance
If transistors are stacked in 3D architecture, then integration density is improved, but electrostatic control of transistors deteriorates
Solution Approach 1:
The patent divides the vertical stack into discrete memory cell levels, each with its own select transistor positioned at a specific altitude. This segmentation allows each transistor to maintain proper electrostatic control over its associated memory cell while contributing to overall high integration density through the stacked arrangement.
Solution Approach 2:
The patent utilizes vertical stacking in the z-dimension to achieve high density while maintaining horizontal spacing and electrostatic control characteristics similar to planar devices. The gate structures extend vertically to provide adequate control over the channel regions despite the stacked configuration.
3Quantity of substance
If conventional 3D memory architecture is used, then density is improved, but current intensity becomes insufficient
Solution Approach 1:
The patent optimizes the local electrical characteristics of each memory cell by positioning select transistors with appropriate channel widths and lengths at specific vertical levels. This local optimization ensures sufficient current intensity for reliable read/write operations while maintaining high overall density through the stacked architecture.
Data Source
AI summary
The invention provides a microelectronic device comprising at least two memory cells each comprising a so-called selection transistor and a memory element associated with said selection transistor, each transistor comprising a channel in the form of a wire extending in a first direction (x), a gate bordering said channel, a source extending in a second direction (y), and a drain connected to the memory element, said transistors being stacked in a third direction (z) and each occupying a given altitude level in the third direction (z), the microelectronic device wherein the source and the drain are entirely covered by spacers projecting in the third direction (z) in a plane (xy). The invention also provides a method for manufacturing such a device.