3D Ferroelectric Memory Cell Layout for Lower Capacitance
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Solution Overview
Problem
Two-dimensional memory devices have reached physical limits in increasing integration, necessitating the development of three-dimensional non-volatile memory devices with memory cells stacked vertically to enhance storage capacity and performance.
Innovation Solution
A three-dimensional memory device is fabricated using ferroelectric memory cells with a semiconductor channel layer, ferroelectric layer, word lines, bit lines, and source/select lines, where the gate electrodes, drain electrodes, and source electrodes extend vertically, and a low-k dielectric material is used to reduce capacitance between conductive structures, improving operation speed and scalability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If the channel layer width is increased to improve operation speed, then the capacitance between the channel layer and adjacent conductive structures increases, which deteriorates performance
Solution Approach 1:
A low-k dielectric material is introduced as an intermediary substance between the channel layer and adjacent conductive structures (word lines, bit lines, source lines). This intermediary material reduces the capacitance coupling between these structures, allowing the channel layer width to be increased for faster operation without suffering from excessive capacitance effects.
Solution Approach 2:
The dielectric constant parameter of the material between the channel layer and conductive structures is changed from high-k to low-k. This parameter change directly reduces the capacitance value, enabling wider channel layers to be used while maintaining acceptable capacitance levels and thus improving operation speed without performance deterioration.
2Quantity of substance
If memory cells are stacked vertically to increase integration density, then the device complexity and manufacturing difficulty increase
Solution Approach 1:
The memory device transitions from a two-dimensional planar structure to a three-dimensional vertically stacked structure. Multiple memory cells are arranged along the vertical direction, allowing integration density to increase without proportionally increasing the lateral footprint, thus achieving higher capacity while managing complexity through vertical scaling.
Solution Approach 2:
The vertically stacked memory device is segmented into multiple distinct layers including channel layers, ferroelectric layers, word lines, bit lines, and source lines. Each layer performs a specific function, and this segmentation allows for modular manufacturing processes and simplifies the management of complexity by dividing the three-dimensional structure into manageable two-dimensional fabrication steps.
3Productivity
If the channel layer width is increased to maintain scalability, then the capacitance with adjacent conductive structures increases, affecting performance
Solution Approach 1:
The low-k dielectric material serves as a mediator that allows the channel layer width to be increased for scalability purposes while preventing the harmful capacitance effect from increasing proportionally. This mediator enables the decoupling of channel width scaling from capacitance scaling.
Solution Approach 2:
The patent converts the potentially harmful capacitance effect into a beneficial situation by using low-k dielectric material. The wider channel layer provides better current drive and scalability, while the low-k material compensates for the increased capacitance, effectively turning what would be a harmful effect into an acceptable or even beneficial trade-off for improved scalability and performance.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The solution enables increased operation speed and design improvements for memory arrays without sacrificing size or scalability, effectively addressing the limitations of two-dimensional devices by enhancing storage capacity through vertical stacking.
Implementation Method 1
a low dielectric constant gap is introduced between them, reducing capacitance
Data Source
AI summary
A memory device includes a plurality of first memory cells disposed along a vertical direction. Each of the plurality of first memory cells includes a portion of a first channel segment that extends along the vertical direction and has a first sidewall and a second sidewall. The first and second sidewalls of the first channel segment facing toward and away from a first lateral direction, respectively. Each of the plurality of first memory cells includes a portion of a first ferroelectric segment that also extends along the vertical direction and is in contact with the first sidewall of the first channel segment. A width of the first ferroelectric segment along a second lateral direction is different from a width of the first channel segment along the second lateral direction. The second lateral direction is perpendicular to the first lateral direction.