3D Memory Drain-Select Isolation With Low-k Air-Gap Structures
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current three-dimensional memory devices face challenges in achieving effective dielectric isolation with a low effective dielectric constant for drain-select-level isolation structures, which affects the performance and efficiency of memory devices.
Innovation Solution
The implementation of a three-dimensional memory device structure that includes an alternating stack of insulating and electrically conductive layers, with a drain-select-level isolation structure having an effective dielectric constant less than 3.9, achieved by filling a drain-select-level isolation trench with a dielectric liner and forming air gaps within the trench, allowing for efficient dielectric isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional dielectric materials are used for drain-select-level isolation structures, then manufacturing is easier, but the effective dielectric constant is too high (greater than 3.9), which degrades memory device performance
Solution Approach 1:
The isolation structure uses a composite material system consisting of a low-k dielectric material (such as fluorosilicate glass or organosilicate glass with effective dielectric constant less than 3.9) combined with air gaps. This composite approach achieves the required low effective dielectric constant while maintaining manufacturability through established low-k deposition and patterning processes.
Solution Approach 2:
The low-k dielectric material inherently possesses a porous or nanostructured composition that reduces its effective dielectric constant. The material structure includes voids or low-density regions that lower the overall dielectric constant below 3.9, improving memory device performance without requiring complex manufacturing steps.
2Reliability
If the effective dielectric constant of drain-select-level isolation structures is reduced below 3.9, then memory device performance improves, but the manufacturing complexity increases
Solution Approach 1:
The invention changes the dielectric constant parameter of the isolation material from conventional values (greater than 3.9) to low-k values (less than 3.9). This parameter change is achieved by selecting specific low-k dielectric materials and controlling their deposition parameters, thereby improving memory device performance without significantly increasing design complexity.
3Reliability
If air gaps are formed within the isolation trench, then the effective dielectric constant decreases below 3.9, but the manufacturing precision requirements increase
Solution Approach 1:
The air gaps are formed as part of the low-k dielectric material deposition process itself, rather than as a separate subsequent step. The low-k material is deposited with inherent void formation characteristics, and the air gaps are created during the deposition process, thereby reducing manufacturing precision requirements compared to post-deposition air gap formation methods.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution enhances the performance of three-dimensional memory devices by improving dielectric isolation, leading to increased efficiency and reliability in memory operations.
Implementation Method 1
a drain-select-level isolation structure vertically extending through the drain-select-level electrically conductive layers and having an effective dielectric constant that is less than 3.9
Data Source
AI summary
A three-dimensional memory device includes an alternating stack of insulating layers and electrically conductive layers located over a substrate, an array of memory opening fill structures located within an array of memory openings vertically extending through the alternating stack, and a drain-select-level isolation structure vertically extending through drain-select-level electrically conductive layers between two rows of memory opening fill structures. The drain-select-level isolation structure may comprise a low-k dielectric material or an air gap.