Solid-State Devices TRIZ Cases

Pitch-tuned pixel spacing makes rear windshield driving information readable while preserving through-view visibility for following traffic.

Separate fluorescent and phosphorescent emission layers with an exciton control layer to improve WOLED color balance, brightness, and efficiency.

Non-uniform FET widths balance parasitic capacitances between neighboring RF switch stacks, preventing top-FET breakdown without added capacitors.

Stacked OLED emitting layers with TADF guest materials improve energy transfer, curb exciton annihilation, and extend display lifetime.

Using a 10-30 nm MoW bit line electrode helps dense IC wiring resist corrosion and surface-scattering resistance increases.

Pocketed micro-devices embed non-native components through the substrate to cut footprint while preserving precise placement and optical access.

Staggered connection lines in adjacent tiled panels cut electrical interference and make display boundaries less visible for better immersion.

A corner encapsulation base layer and sealant-overlap line layout improve OLED sealing adhesion and reduce water-oxygen corrosion risk.

Shared reset and select transistors let compact image sensor pixels support HCG, DCG, and TCG modes for wider dynamic range.

A porous protrusion and stacked impurity intermediate layer boost light extraction, curb surface leakage current, and reduce separation damage.

A filling block in the insulating-layer via hole improves film flatness, cuts light leakage, and preserves display aperture ratio.

Laminated semiconductor layers increase near-infrared sensitivity without deep implantation or repeated epitaxial growth, cutting process complexity.

Isolation structures and rod semiconductor layers shrink sub-pixels while limiting light leakage for sharper micro LED color displays.

A single non-intersecting layer for grounding, power, and chip I/O wiring reduces short circuits, simplifies fabrication, and improves yield.

A folded 3D SOI stack with heavily doped layers and discharge metal paths dissipates fabrication charge without through-insulator holes.

Two-step pulsed etching shapes tapered cut-gate openings to reduce dielectric voids and improve metal gate isolation and yield.

An electric circuit layer on LED chip backs removes wire bonds, shrinking package size and increasing light exit area for displays.

Heat dissipation holes between the gate driving circuit and sub-pixels conduct heat away to preserve display brightness uniformity.

A backside trench with conductive pads and vias cuts pad-to-pixel step height, improving image quality, yield, and electrical routing.

Backside light blocking structures absorb reflected image beams in a transparent display, reducing leakage while preserving see-through visibility.

Separate inter-die ECC links let DDR5 dies handle longer burst transfers without exceeding TSV tolerance, improving speed and reliability.

A dummy electrode shields transistor semiconductor patterns from transmitted light, improving display panel reliability without losing transmission.

Curved, upward, and inclined bonding wires connect stepped upper and lower die stacks while reducing package size and overhang.

Vertical LED stacks with through-vias connect directly to circuit-board pads, avoiding transfer disconnects and increasing sub-pixel brightness.

A superconductor shunt gives an NIS cooler a low-resistance current path, cutting I^2*R losses and reducing overheating in the leads.

A resin layer and adhesive cover a through-hole conductive layer to slim the wiring body without deforming the mesh or hurting display visibility.

Oblique bank surfaces and scattering particles narrow pixel emission to better match projection lenses and improve AR image brightness.

A graded metal-oxide conductive stack lowers interlayer contact resistance, reducing voltage drop and stabilizing signal transmission in display panels.

In-line resin viscosity sensing flags deterioration before coating, helping maintain protective layer thickness and fixing force during stacking.

Grouping micro-LEDs into macro-pixels shares drive circuits, enabling higher bit depth and lower current variation at small pixel pitch.

Using the pixel electrode pattern as the touch sensing electrode removes a separate layer, cutting display cost, process steps, and thickness.

Stacked transparent conductive sub-layers route more lines to under-screen pixels, enlarging the camera region while preserving light transmittance.

Liquid-filled grooves and absorber scanning align micro-semiconductor chips accurately, improving transfer yield for small micro-LEDs on large displays.

Microwave annealing shifts zirconium oxide to a tetragonal phase, raising DRAM capacitor capacitance without increasing leakage or cost.

Shared output terminals for two TFTs reduce channel-length deviation effects, improving VA-mode LCD brightness uniformity and smudge control.

Patterned light control cuts light toward the windshield, reducing reflected display images and Moiré interference for safer driving.

A dielectric stress recovery layer protects the micro LED epitaxial layer during laser lift-off, preventing cracks and coarsening damage.

A 3D light-absorbing layer spans module surfaces and gaps to suppress diffused reflection, hide lattice lines, and keep the screen continuous.

A matching jig fixed with dicing tape balances blade load during wafer orientation flat cutting, reducing breakage risk and blade wear.

An epitaxial planar converter layer boosts μLED wavelength conversion while reducing edge recombination losses, crosstalk, and RGB control mismatch.

Irregular pores filled with a light conversion unit improve light output and quality while keeping the structure compact and easier to manufacture.

Separated thin and thick horizontal lines cut interconnect capacitance, improving high-speed pixel signal readout and image quality.

A stacked sensor layout shares pixel transistors and consolidates contacts to cut substrate area while supporting higher pixel density.

Different gate oxide thicknesses on one active region preserve equal source/drain depth, improving memory density and reliability.

A physically disconnected cathode in light-transmitting display areas enables low-energy laser patterning, limits edge curling, and blocks moisture paths.

A multilayer insulating layer and biased conductive pattern block pixel leakage currents while keeping emission areas closely spaced.

An intermediate band layer with dopant particles lets silicon detect beyond 1100 nm, extending IR sensitivity without costly materials.

A multilayer insulating layer and biased conductive pattern block leakage currents between display pixels while supporting tighter pixel spacing.

Grouped LEDs under a common diffusion layer improve cockpit display lifespan, redundancy, and retrofit compatibility with existing resolutions.

Stacking memory, decoder, and control chips with different transistor channel lengths cuts package width while preserving voltage fit and signal transmission.