Inter-Die ECC Connectors for DDR5 Burst-Length Transfer Limits
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Solution Overview
Problem
The increased burst length in DDR5 memory devices exceeds the tolerances of existing inter-die connectors like through-silicon vias (TSVs), potentially leading to data transfer issues and errors.
Innovation Solution
The implementation of separate inter-die error correction connectors, in addition to the existing inter-die data connectors, allows for the efficient transfer of read and write data bits and associated error correction information between a master die and target dies in DDR5 memory devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the burst length is increased to sixteen in DDR5, then the data transfer capacity is improved, but the clock speed exceeds the tolerances of inter-die connectors
Solution Approach 1:
The patent divides the data transfer path into separate channels: one for data bits and another for error correction information. This segmentation allows data to be transmitted at higher rates while error correction follows at a manageable pace, resolving the contradiction between increased data transfer capacity and connector tolerance limitations.
Solution Approach 2:
The patent introduces separate error correction connectors as an intermediary mechanism that handles error correction information independently from the main data path. This mediator allows the data channel to operate at high speeds while the error correction channel operates at tolerable speeds, resolving the tension between productivity and reliability.
2Reliability
If separate error correction connectors are implemented, then data transfer reliability is improved, but device complexity increases
Solution Approach 1:
By segmenting the connector architecture into dedicated data connectors and error correction connectors, the patent improves reliability through specialized pathways while keeping each individual connector simple and manageable, thus balancing reliability improvement with controlled complexity.
Solution Approach 2:
The separate error correction connectors, while adding structural elements, enable the system to handle multiple functions (data transfer and error correction) through dedicated pathways, which ultimately simplifies the overall system operation and reduces the complexity of error handling in the main data path.
Data Source
AI summary
Apparatuses for transfer of data and error correction between semiconductor dies are disclosed. An apparatus may include a number of dies including a first die and a second die. The first die may be configured to receive data bits and error correction information from the second die via inter-die connectors. The first die may further be configured to generate new error correction information corresponding to the data bits via the error correction circuitry. Further, the first die may be configured to write the data bits to data storage elements responsive to a determination that the error correction information matches the new error correction information.