ESD Protection Circuit Using DMOS and IGBT Transistors
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The existing ESD protection techniques for semiconductor integrated circuit devices with high voltage terminals require larger transistors to increase current capacity and breakdown strength, leading to increased chip area and costs due to the higher ratio of ESD protection elements, which is inefficient in terms of layout and cost.
Innovation Solution
The proposed solution involves an ESD protection circuit with multiple clamping circuits and transistors, including DMOS and IGBT, where the DMOS transistor absorbs small current noise to prevent latch-up and the IGBT with thyristor effect handles high current, allowing for increased ESD withstand voltage without increasing the circuit size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the size of the transistor is increased to increase current capacity and breakdown strength, then ESD withstand voltage is improved, but the layout area of the ESD protection circuit increases
Solution Approach 1:
The patent divides the ESD protection circuit into multiple functional segments: a first clamping circuit (Zener diodes 106-110) for voltage clamping, a second clamping circuit (Zener diodes 103-104) for gate protection, and multiple transistors (101, 111-115) for current absorption. This segmentation allows each component to be optimized for its specific function rather than requiring a single large transistor to handle all ESD protection functions, thereby reducing the overall layout area while maintaining high ESD withstand voltage.
Solution Approach 2:
The patent employs transistors with dual functionality: they serve as both switching elements for normal circuit operation and as ESD protection elements when activated. The transistors (101, 111-115) are configured to remain inactive during normal operation but automatically activate to absorb ESD current when voltage exceeds safe thresholds. This multi-functionality eliminates the need for dedicated ESD protection components, reducing layout area while improving ESD withstand voltage.
2Reliability
If more ESD protection components are added to improve ESD withstand voltage, then reliability is improved, but the ratio of ESD protection element area to entire chip area increases
Solution Approach 1:
The patent merges ESD protection functionality with the main circuit transistors. The transistors (101, 111-115) that are part of the normal circuit operation are configured to also serve as ESD protection elements. By combining these functions, the patent avoids adding separate dedicated ESD protection components, thereby maintaining a low ratio of ESD protection element area to entire chip area while achieving high ESD withstand voltage through the coordinated action of multiple clamping circuits and transistors.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances ESD withstand voltage performance while reducing the layout area required for the ESD protection circuit, improving semiconductor integrated circuit device performance without increasing its size, thus addressing the inefficiencies of existing solutions.
Implementation Method 1
The Zener diodes 103 and 104 for limiting the gate voltage of the transistor 101 to the gate withstand voltage
Implementation Method 2
The transistor 101 is comprised of a double diffused metal oxide semiconductor (DMOS) which absorbs ESD current
Implementation Method 3
the IGBT with thyristor effect handles high current
Data Source
AI summary
The present invention provides a technique capable of realizing an ESD protection performance having a high ESD withstand voltage in a small layout area. An ESD protection circuit includes a clamping circuit, Zener diodes, a transistor comprised of a DMOS, a transistor comprised of an IGBT, and resistors. The ESD protection circuit effectively protects the protected circuit such that the transistor comprised of the DMOS is caused to absorb the current noise at the time of operating the protected circuit to prevent malfunction due to latchup and the IGBT (the transistor comprised of IGBT) whose current absorption capacity is increased by the thyristor effect is operated in parallel for a large current at the time of ESD.