Semiconductor Device Stress Relaxation Structure
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Solution Overview
Problem
The integration density of conventional two-dimensional semiconductor memory devices is limited by the high cost of equipment for forming fine patterns, and there is a need for more cost-effective methods to increase integration density while maintaining performance.
Innovation Solution
A semiconductor device with a logic section, a memory section, and a stress relaxation section is proposed, where the memory section is stacked above the substrate with semiconductor memory elements, and the stress relaxation section alleviates stress between the logic and memory sections, allowing for efficient data storage and connection.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If three-dimensional stacking is used to increase integration density, then integration density is improved, but stress between layers increases causing device deterioration
Solution Approach 1:
A stress relaxation structure is introduced as an intermediary element between the logic circuit and memory structure. This stress relaxation structure includes a first cavity and a second cavity that are selectively formed to release stress accumulated in the stacked configuration, thereby preventing device deterioration while maintaining high integration density.
Solution Approach 2:
The patent changes the physical parameters of the device structure by creating cavities (void spaces) within the stacked layers. These cavities alter the mechanical properties of the structure, providing stress relaxation pathways that accommodate thermal expansion and mechanical stress without compromising the electrical functionality or integration density.
2Productivity
If fine pattern techniques are advanced to increase integration density in 2D devices, then integration density is improved, but manufacturing cost increases
Solution Approach 1:
The patent transitions from two-dimensional planar memory cells to three-dimensional stacked memory structures. By utilizing the vertical dimension, the device achieves higher integration density without requiring finer lateral patterning, thereby avoiding the increased manufacturing costs associated with advanced 2D patterning techniques.
3Reliability
If stress relaxation structures are added to relieve stress, then device reliability is improved, but structural complexity increases
Solution Approach 1:
The stress relaxation structure is segmented into multiple cavities (first cavity and second cavity) that are selectively positioned at different locations within the stacked structure. This segmentation allows stress relaxation to occur at specific high-stress points without requiring a complete structural redesign of the entire device, thereby managing complexity effectively.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances integration density and reduces manufacturing costs by utilizing a stress relaxation structure to mitigate stress-related deterioration, thereby improving the performance and reliability of the semiconductor device.
Implementation Method 1
a stress relaxation section interposed between the logic section and the memory section in the circuit region and is composed to relieve stress which would otherwise be present in the device due to at least the stack of layers of the memory section
Data Source
AI summary
A semiconductor device includes a logic structure including a logic circuit disposed in a circuit region and a lower insulation covering the logic circuit, a memory structure on the logic structure, a stress relaxation structure interposed between the logic structure and the memory structure in the circuit region, and a connection structure electrically connecting the memory structure to the logic circuit along a conductive path that extends through a connection region of the device beside the circuit region.