3T and 4T FinFET Height Differential for Simultaneous Fabrication
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Solution Overview
Problem
The challenge in semiconductor technology is the high static power consumption of integrated circuits due to transistor short-channel effects, which is difficult to address through simultaneous production of 3T-FinFET and 4T-FinFET on the same wafer using conventional methods.
Innovation Solution
A method is developed to form 3T-FinFET and 4T-FinFET on a semiconductor substrate by creating a height difference between fins, allowing for the simultaneous formation of these devices by pre-defining the height difference between the first and second fins, ensuring the second gate remains intact during the removal process, thereby simplifying the manufacturing process and improving efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If conventional methods are used to produce 3T-FinFET and 4T-FinFET on the same wafer, then manufacturing complexity increases, but production efficiency decreases
Solution Approach 1:
The patent applies preliminary action by pre-defining the height difference between first and second fins during the fin formation stage. This preliminary structural differentiation enables subsequent selective gate removal processes to automatically distinguish between 3T-FinFET and 4T-FinFET regions, eliminating the need for complex post-processing steps and mask alignments that would otherwise be required to produce both device types on the same wafer.
2Adaptability or versatility
If the second gate is removed during processing, then 3T-FinFET structure is achieved, but the 4T-FinFET structure cannot be maintained on the same wafer
Solution Approach 1:
The patent applies local quality by making the fin height a localized structural characteristic that varies between first fins (for 3T-FinFET) and second fins (for 4T-FinFET). This localized height difference enables selective access to the second gate: in regions with shorter second fins, the second gate can be removed to form 3T-FinFET, while in regions with taller second fins, the second gate remains intact to form 4T-FinFET, all within the same wafer processing sequence.
3Ease of manufacture
If height difference between fins is not pre-defined, then fins are at the same level, but selective gate removal becomes impossible
Solution Approach 1:
The patent applies dimensionality change by introducing height as a critical dimension for fin structure differentiation. Instead of using planar variations or lateral positioning to distinguish between 3T-FinFET and 4T-FinFET regions, the invention uses the vertical dimension (fin height) as the distinguishing feature. This enables simple planar processing steps to selectively access and remove second gates based on height differences, converting a potentially complex 3D selective removal problem into a straightforward 2D planar process.
Data Source
AI summary
Semiconductor devices and fabrication methods for simultaneously forming a 3T-FinFET and a 4T-FinFET on a same substrate are provided. A first fin and a second fin can be formed on a semiconductor substrate. The first fin has a top surface higher than the second fin. A first gate dielectric layer and a first gate can be formed across the first fin. A second gate dielectric layer and a second gate can be formed across the second fin. An interlayer dielectric layer can be formed to cover the first gate, the second gate, and the semiconductor substrate. A first portion of the interlayer dielectric layer, a portion of the first gate, and a portion of the first gate dielectric layer, over the first fin, and a second portion of the interlayer dielectric layer over the second fin can be removed to expose the second gate.