Variable Resistance Element Spacer Alignment for Etching Contamination
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Solution Overview
Problem
Current semiconductor memory devices face challenges in improving the characteristics and processes of variable resistance elements, particularly in the formation of MTJ structures, which can lead to defects such as increased write error rates and shunt failures due to conductive by-products during etching processes.
Innovation Solution
The proposed solution involves a semiconductor device with a variable resistance element that includes a lower electrode, a spacer, and a variable resistance pattern, where the spacer has a recessed external sidewall aligned with the upper portion of the lower electrode and the variable resistance pattern, effectively reducing contamination and improving the structure's integrity during the etching process.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional etching processes are used for MTJ structure formation, then manufacturing process can be simplified, but conductive by-products cause increased write error rates and shunt failures
Solution Approach 1:
The patent extracts and removes conductive by-products from the etching process through a dedicated cleaning step using ICP (Inductively Coupled Plasma) treatment. This separates the harmful by-products from the final device structure, eliminating their negative impact on write error rates while maintaining the simplicity of the conventional etching process.
Solution Approach 2:
The patent introduces an intermediary cleaning process using ICP treatment between the etching steps and final device formation. This intermediary step acts as a mediator that removes conductive by-products without interfering with the primary etching function, thereby resolving the contradiction between process simplicity and device reliability.
2Reliability
If conventional MTJ structure formation is used, then device complexity is reduced, but shunt failures increase due to contamination
Solution Approach 1:
The patent converts the harmful effect of conductive by-products into a beneficial process by using ICP treatment to deliberately remove these by-products. The same plasma technology that could potentially cause damage is used in a controlled manner to clean and purify the structure, transforming a harmful factor into a useful cleaning mechanism that reduces shunt failures.
Solution Approach 2:
The patent replaces mechanical cleaning methods with a plasma-based chemical cleaning process. Instead of using physical removal techniques that might damage the delicate MTJ structure, the ICP process uses controlled chemical reactions to remove contaminants, thereby maintaining structural integrity while reducing shunt failures.
3Manufacturing precision
If metallic materials are not removed during etching, then production efficiency is maintained, but contamination increases on the variable resistance pattern
Solution Approach 1:
The patent performs preliminary cleaning action during the etching process itself by using ICP treatment to remove metallic by-products as they are formed. This preliminary removal prevents contamination accumulation before it affects the variable resistance pattern, thereby maintaining high manufacturing precision without requiring additional post-processing steps that would reduce production efficiency.
Data Source
AI summary
An electronic device may include a semiconductor memory, and the semiconductor memory may include a variable resistance element. The variable resistance element may include a lower electrode; a spacer formed on a side surface of the lower electrode; and a variable resistance pattern disposed over the lower electrode, wherein a portion of the lower electrode covers a top surface of the spacer.