Dual Gate Memory Devices With Distinct Threshold Voltages
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
Current memory systems face challenges in achieving efficient and accurate operation, particularly in storing multiple bits in a compact layout and regulating input voltage/current for magnetic memory devices across varying temperatures without excessive power consumption.
Innovation Solution
Dual threshold voltage devices are implemented, featuring a first and second charge storage device with distinct threshold voltages, configured to store multiple bits and selectively supply currents to magnetic memory components based on temperature, using parallel transistors and control circuitry to manage bit error rates.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If conventional memory systems are used, then simplicity is maintained, but storage density and performance are insufficient
Solution Approach 1:
The memory device is segmented into two distinct charge storage devices (first and second charge storage devices) with different threshold voltages. Each charge storage device can independently store one bit of data, enabling the storage of two bits per memory device. This segmentation increases storage density while maintaining manageable device complexity through modular design.
Solution Approach 2:
The memory device structure is designed to be multi-functional, serving both as a high-density storage unit and as a temperature-compensating device for magnetic memory. The parallel configuration of the two charge storage devices allows the system to universally handle both data storage and voltage regulation functions, improving storage density without proportionally increasing complexity.
2Reliability
If temperature compensation circuitry is added to magnetic memory devices, then bit error rate is improved, but power consumption increases
Solution Approach 1:
The system changes the threshold voltage parameter of the charge storage devices based on temperature conditions. The first charge storage device with a first threshold voltage and the second charge storage device with a second threshold voltage are selectively activated to compensate for temperature-induced variations in magnetic memory operation. This parameter adjustment improves bit error rate while maintaining efficient power consumption by only activating the necessary charge storage device for current temperature conditions.
Solution Approach 2:
Different regions of the memory system are assigned different threshold voltage characteristics. The first charge storage device is optimized for certain temperature ranges while the second charge storage device is optimized for other ranges. This local quality differentiation allows temperature compensation to be applied precisely where needed, improving reliability without excessive power consumption across the entire system.
3Quantity of substance
If dual threshold voltage devices are used, then storage density and temperature compensation are achieved, but device complexity increases
Solution Approach 1:
The patent merges multiple functions into a single integrated memory device structure. The first and second charge storage devices are combined in parallel within the same memory device, allowing simultaneous achievement of high storage density (2 bits per device) and temperature compensation capability. This merging approach increases storage density while controlling device complexity through functional integration rather than separate components.
4Quantity of substance
If compact memory layout is implemented, then storage density is improved, but manufacturing precision requirements increase
Solution Approach 1:
The compact memory layout is achieved through segmentation of the memory device into two distinct charge storage devices with clearly defined boundaries and separate threshold voltage characteristics. This segmentation allows for modular manufacturing processes where each charge storage device can be fabricated with standard precision requirements, yet the overall device achieves high storage density through the parallel configuration of the segmented units.
Data Source
AI summary
The various implementations described herein include methods, devices, and systems for performing operations on memory devices. In one aspect, a memory device includes: (1) a first charge storage device having a first gate with a corresponding first threshold voltage, the first charge storage device configured to store charge corresponding to one or more first bits; and (2) a second charge storage device having a second gate with a corresponding second threshold voltage, distinct from the first threshold voltage, the second charge storage device configured to store charge corresponding to one or more second bits; where the second charge storage device is coupled in parallel with the first charge storage device.