Vertical Gate Cell Structure for Semiconductor Memory Devices
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Solution Overview
Problem
Conventional semiconductor memory devices using diodes as switching devices face increased resistance in word lines and bit lines with further integration, leading to reduced read/write sensing margins and increased internal operation voltage, along with complex fabrication processes and higher production costs.
Innovation Solution
The implementation of a vertical gate cell structure, where a gate cell material layer is formed on a bit line, etched, and spacer insulating layers are used to create a trench for forming a gate oxide and metal layer, resulting in a floating word line that increases voltage and reduces power consumption, while simplifying the fabrication process and lowering costs.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If diode is used as switching device with individually separated word lines and bit lines, then cell selection is achieved, but resistance of word line increases with further integration leading to reduced read/write sensing margin
Solution Approach 1:
The patent transitions from a planar layout with individually separated word lines to a vertical gate cell structure where the word line is formed as a floating gate extending in the vertical dimension. This dimensional change allows the word line to serve multiple cells simultaneously without increasing resistance, as the floating gate structure provides better electrical connection and reduced parasitic resistance compared to traditional separated word lines.
Solution Approach 2:
The patent merges multiple word line functions into a single floating gate structure that serves multiple memory cells. Instead of having individually separated word lines for each cell, the floating gate is shared across multiple cells, reducing the total number of word lines and their associated resistance, while still enabling cell selection through the vertical gate cell architecture.
2Area of stationary object
If critical dimensions of word line and bit line are reduced for further integration, then device size is reduced, but interconnection line resistance increases and internal operation voltage increases
Solution Approach 1:
The patent employs vertical gate cells that extend in the vertical dimension, allowing critical dimensions in the planar direction to be reduced for better integration while maintaining adequate current flow paths vertically. The floating gate structure provides robust electrical connections that compensate for the reduced planar dimensions, preventing interconnection resistance from increasing despite smaller device footprint.
3Reliability
If diode is formed as switching device, then cell selection is achieved, but all mask processes are performed with cell pitch making fabrication process complicated and production cost increased
Solution Approach 1:
The patent uses vertical gate cells that extend in the vertical dimension, allowing mask processes to be performed with larger pitch in the planar direction. The vertical extension of the gate cell structure provides the necessary cell selection capability without requiring all mask processes to be performed at the minimum cell pitch, thereby simplifying the fabrication process and reducing production costs while maintaining reliable cell selection.
Data Source
AI summary
A semiconductor memory device comprising a bit line extending in a first direction, a vertical gate cell including a gate oxide layer and a gate metal layer that are formed in a pillar shape, a lower electrode and a data storage material layer formed on the vertical gate cell, and an interconnection layer formed on the data storage material layer.