3D NAND Memory Sub-Block Erase via Segmented Reference Lines
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Solution Overview
Problem
Conventional 3D NAND flash memory architectures face limitations in memory management due to large erase block sizes, which increase memory management time and reduce memory cell endurance, as they require all NAND strings in a block to be biased equally during erase operations, limiting flexibility and efficiency.
Innovation Solution
The introduction of a memory device structure that supports sub-block erase operations, where each block is coupled to multiple reference lines, allowing for independent biasing of sub-blocks within a block, enabling selective erase operations by applying distinct biases to reference lines and maintaining common biases for bit lines, string select lines, and word lines.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of time
If conventional NAND flash architecture with single reference line per block is used, then device complexity is reduced, but erase block size becomes large leading to increased memory management time
Solution Approach 1:
The patent divides a single reference line into multiple independent reference lines (first reference line and second reference line), allowing different sub-blocks within a block to be connected to different reference lines. This segmentation enables independent biasing of sub-blocks, facilitating smaller erase units and reducing memory management time while maintaining reasonable device complexity through systematic organization.
Solution Approach 2:
The patent introduces a new dimension of organization by creating multiple reference lines within a block rather than simply increasing the number of blocks. This dimensional change in the reference line structure allows for finer-grained control of erase operations without proportionally increasing overall device complexity, as the multiple reference lines share common control circuitry and routing structures.
2Productivity
If larger block size is used, then number of blocks is reduced, but memory management time increases
Solution Approach 1:
By segmenting the reference line into multiple independent lines, the patent enables division of a block into smaller sub-blocks that can be erased independently. This segmentation allows memory management operations to work with smaller units, improving efficiency and reducing the time required for memory management tasks such as wear leveling and garbage collection.
Solution Approach 2:
The patent creates a dynamic architecture where the erase unit size can be flexibly adjusted by selectively activating different reference lines and their associated sub-blocks. This dynamic capability allows the memory system to adapt erase operations to actual needs, improving productivity by avoiding unnecessary erasure of entire large blocks when only small portions need to be managed.
3Reliability
If larger block size is used, then number of blocks is reduced, but endurance is reduced due to increased program and erase cycling
Solution Approach 1:
The patent segments each block into multiple sub-blocks associated with different reference lines, enabling selective erasure of only the necessary sub-blocks rather than entire blocks. This segmentation reduces the frequency of program and erase cycling for any given memory cell, thereby improving endurance while maintaining an adequate number of blocks for memory management purposes.
Solution Approach 2:
The patent enables more efficient recovery and reuse of memory space by allowing partial erasure of blocks. When only certain sub-blocks need to be erased, the remaining sub-blocks can be immediately reused, reducing the overall cycle count and improving endurance while maintaining productivity through faster space recovery.
4Loss of time
If sub-block erase is enabled, then erase unit size is reduced, but reference line structure complexity increases
Solution Approach 1:
The patent implements segmentation of the reference line into multiple independent lines, which directly enables sub-block erase functionality. This segmentation allows different portions of a block to be erased independently, reducing erase operation time for partial block erasures while keeping the structural complexity manageable through systematic organization and shared control circuitry.
Solution Approach 2:
The multiple reference lines are designed with universal characteristics, sharing common control logic, routing structures, and connection methods. This multi-functionality approach allows the same structural patterns to be reused across different reference lines, enabling sub-block erase capability without proportionally increasing overall device complexity.
Data Source
AI summary
A memory device has a divided reference line structure which supports sub-block erase in NAND memory including a plurality of blocks. Each block in the plurality of blocks is coupled to a set of Y reference lines, where Y is two or more. Each block in the plurality of blocks includes a single reference select line (RSL), which is operable to connect each sub-block in the block to a corresponding reference line in the set of Y reference lines. A control circuit can be included on the device which is configured for an erase operation to erase a selected sub-block in a selected block.