Doped Semiconductor Channel for 3D Memory Contact Resistance
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The challenge in 3D memory devices is the high contact resistance between the semiconductor channel and the sidewall selective epitaxial growth (SEG) or conductive layers, which affects the electric performance due to the use of intrinsic semiconductor materials, leading to increased process complexity and costs in advanced technologies like 90+ level multi-deck architectures.
Innovation Solution
The introduction of a doped semiconductor channel with a highly doped portion to reduce the potential barrier, combined with a doped semiconductor layer that electrically connects the exposed doped parts of the semiconductor channels, reduces contact resistance and sheet resistance, improving the electric performance by enhancing the gate-induced drain leakage (GIDL) effect and increasing the contact area.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If intrinsic semiconductor materials are used in the channel structure, then the manufacturing process is simpler, but the contact resistance between the channel and conductive layers increases significantly
Solution Approach 1:
The patent applies local quality by introducing doped semiconductor layers specifically at the contact regions between the channel structure and conductive layers, while the bulk channel structure can remain with simpler intrinsic material. This localized doping approach reduces contact resistance at critical interfaces without requiring the entire channel to be complex doped structure, thus resolving the contradiction between manufacturing simplicity and contact resistance.
Solution Approach 2:
The patent changes the doping parameter of the semiconductor material from intrinsic (undoped) to doped state in specific regions. By controlling the doping concentration and distribution in the semiconductor layers adjacent to conductive layers, the electrical properties are modified to reduce contact resistance and sheet resistance, directly addressing the reliability issue while maintaining manufacturing feasibility through controlled parameter changes.
2Reliability
If the contact area between semiconductor channel and conductive layers is increased, then the contact resistance decreases, but the device structure becomes more complex
Solution Approach 1:
The patent merges the semiconductor channel structure with additional doped semiconductor layers to form an integrated contact structure. By combining the channel-forming semiconductor material with doped semiconductor layers in a unified structure, the contact area is increased and contact resistance is reduced without requiring separate discrete components or complex assembly processes, thus improving reliability without proportionally increasing device complexity.
3Reliability
If doped semiconductor layers are added to reduce contact resistance, then the electrical performance improves, but the manufacturing process complexity increases
Solution Approach 1:
The patent incorporates doped semiconductor layers during the initial formation of the channel structure, before subsequent processing steps. By preliminarily establishing the doped regions that will reduce contact resistance, the need for additional complex post-processing steps is minimized. The doping is integrated into the existing manufacturing flow, improving electrical performance while limiting the increase in process complexity through preliminary action.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This solution effectively reduces contact resistance and enhances the electric performance of 3D memory devices, improving erase speed, reducing current consumption, and lowering power consumption by ensuring consistent doping concentrations across the channel and semiconductor layers.
Implementation Method 1
The introduction of a doped semiconductor channel with a highly doped portion to reduce the potential barrier
Implementation Method 2
reduces contact resistance and sheet resistance, improving the electric performance
Data Source
AI summary
Three-dimensional (3D) memory devices and methods for forming the same are disclosed. In certain aspects, a stack structure includes interleaved dielectric layers and conductive layers, a channel structure extending in the stack structure, and a doped semiconductor layer arranged on the stack structure. The doped semiconductor layer covers an end of the channel structure and the stack structure, the channel structure includes a channel layer, and the channel layer includes a doped channel layer.