Stacked NOR Flash TFT Strings With Vertical Gates for Low-Latency Reads
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Solution Overview
Problem
Existing high-density memory structures, such as NAND strings, face limitations in read-latency, program-disturb, and read-disturb conditions due to high series resistance and low channel mobility of polysilicon thin-film transistors, which restrict the number of transistors in a string and increase latency.
Innovation Solution
Organizing multi-gate NOR flash thin-film transistor strings as stacks of horizontal active strips with vertical local word-lines, allowing only activated transistors to be read or programmed, reducing series resistance and eliminating program-disturb conditions, and achieving higher storage density by storing multiple bits per transistor.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If NAND strings are used with series-connected TFTs, then storage density can be increased, but program-disturb and read-disturb conditions occur and read latency increases
Solution Approach 1:
The patent divides the memory string into parallel NOR string structures where each string can be independently accessed. Instead of series-connected TFTs as in NAND, the invention uses parallel connections with independent word line control, allowing selective activation of individual TFTs without affecting others in the same string.
Solution Approach 2:
The patent inverts the conventional NAND approach by using NOR string architecture with parallel connections instead of series connections. This inversion allows individual TFTs to be read or programmed without activating the entire string, thereby eliminating program-disturb and read-disturb conditions while maintaining high storage density.
2Ease of manufacture
If polysilicon thin-film transistors are used, then manufacturing simplicity is improved, but channel mobility is low and series resistance is high
Solution Approach 1:
The patent changes the geometric parameters of the TFT structure by implementing short channel lengths and optimized channel widths to compensate for the low mobility inherent in polysilicon devices. The parallel NOR string configuration also allows for reduced effective resistance by providing multiple parallel conduction paths.
3Quantity of substance
If long NAND strings are used, then storage density is improved, but read current resistance increases and latency increases
Solution Approach 1:
The patent segments the memory architecture into multiple parallel NOR strings that can be independently accessed. This segmentation allows the read current to be distributed across multiple parallel paths rather than flowing through a single long series string, thereby reducing the effective resistance and latency while maintaining high storage density.
Data Source
AI summary
Multi-gate NOR flash thin-film transistor (TFT) string arrays (“multi-gate NOR string arrays”) are organized as stacks of horizontal active strips running parallel to the surface of a silicon substrate, with the TFTs in each stack being controlled by vertical local word-lines provided along one or both sidewalls of the stack of active strips. Each active strip includes at least a channel layer formed between two shared source or drain layers. Data storage in the TFTs of an active strip is provided by charge-storage elements provided between the active strip and the control gates provided by the adjacent local word-lines. Each active strip may provide TFTs that belong to one or two NOR strings, depending on whether one or both sides of the active strip are used.