3D Memory Gate Leakage Control via Doped Silicate Pillars
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Solution Overview
Problem
Current three-dimensional memory devices face challenges in effectively controlling gate-induced drain leakage current, which affects the performance and efficiency of memory storage.
Innovation Solution
The development of a three-dimensional memory device structure involving a source contact layer, alternating stacks of insulating and conductive layers, memory openings filled with a semiconductor channel and doped silicate glass pillars, and the conversion of semiconductor channels into source regions to manage drain leakage current.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional three-dimensional memory device structures are used, then manufacturing is simpler, but gate-induced drain leakage current control is insufficient
Solution Approach 1:
The source contact layer is segmented into multiple regions including a first source region, a second source region, and a third source region at different vertical levels. This segmentation allows independent control and optimization of current flow paths at each level, improving gate-induced drain leakage current control while managing device complexity through modular design
Solution Approach 2:
The patent implements a nested structure where alternating stacks of insulating and conductive layers are positioned over the source contact layer, and memory openings with fill structures are nested within these stacks. The doped silicate glass pillars are nested within the memory opening fill structures, creating a hierarchical nested arrangement that enhances leakage control without excessive complexity increase
2Manufacturing precision
If semiconductor channels are converted into source regions, then source region formation is optimized, but manufacturing process complexity increases
Solution Approach 1:
Doped silicate glass pillars are formed in advance within the memory openings before the semiconductor channel material is deposited. These pre-formed doped regions serve as nucleation sites for subsequent source region formation, ensuring precise dopant placement and improving manufacturing precision while streamlining the overall process
Solution Approach 2:
The semiconductor channel material automatically converts into source regions through self-doping mechanisms where dopants from the pre-formed doped silicate glass pillars diffuse into the channel material during subsequent processing steps. This self-service approach eliminates the need for separate source region doping steps, improving precision without proportionally increasing process complexity
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enhances the control over gate-induced drain leakage current, improving the memory device's performance and efficiency by optimizing the semiconductor channel and source region formation.
Implementation Method 1
converting a lower portion of each semiconductor channel into a source region by outdiffusing dopants from the doped silicate glass pillars to adjacent portions of the semiconductor channels
Data Source
AI summary
An alternating stack of insulating layers and sacrificial material layers is formed over a substrate. Memory openings are formed through the alternating stack. A layer stack including a charge storage layer, a tunneling dielectric layer, a semiconductor material layer, and a dielectric material layer is formed in the memory openings. The dielectric material layer may include a doped silicate glass layer. A doped silicate glass pillar can be formed at a bottom portion of each memory opening, and a bottom portion of the semiconductor material layer can be converted into a source region by outdiffusion of dopants from the doped silicate glass pillar. Alternatively, the semiconductor material layer can be heavily doped, and can be recessed to form a source region.