Stacked Image Sensor Layout for Full Well Capacity

Solution Overview

Problem

As pixel regions in image sensor integrated chips decrease in size, the full well capacity (FWC) decreases, leading to saturation of photodiodes in bright light conditions, affecting image sensor performance and auto focus functionality.

Innovation Solution

The image sensor integrated chip structure features image sensing elements on a separate substrate from pixel support devices, allowing for larger pixel regions and utilizing interconnect structures to couple them, enabling design freedom for different configurations.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If pixel regions are decreased in size to increase pixel density, then the number of pixels per unit area increases, but the full well capacity decreases leading to photodiode saturation in bright light conditions

Engineering Contradiction:

Improvepixel densityVSAvoidfull well capacity

Core Design Contradiction:

Quantity of substanceVSReliability

Solution Approach 1:

The patent divides the image sensor into multiple separate tiers: a first tier containing pixel support devices and a second tier containing image sensing elements. This segmentation allows each tier to be optimized independently, enabling larger pixel regions in the second tier while maintaining high pixel density through the multi-tier architecture.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent transitions from a planar two-dimensional layout to a three-dimensional stacked architecture. By stacking the pixel support devices and image sensing elements in separate tiers vertically, the system achieves higher pixel density in the vertical dimension while maintaining larger horizontal pixel region sizes, thus resolving the contradiction between pixel density and full well capacity.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Reliability

If pixel regions are increased in size to improve full well capacity, then photodiode saturation is reduced, but the number of pixels per unit area decreases

Engineering Contradiction:

Improvefull well capacityVSAvoidpixel density

Core Design Contradiction:

ReliabilityVSQuantity of substance

Solution Approach 1:

The patent divides the image sensor into multiple separate tiers: a first tier containing pixel support devices and a second tier containing image sensing elements. This segmentation allows each tier to be optimized independently, enabling larger pixel regions in the second tier while maintaining high pixel density through the multi-tier architecture.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent transitions from a planar two-dimensional layout to a three-dimensional stacked architecture. By stacking the pixel support devices and image sensing elements in separate tiers vertically, the system achieves higher pixel density in the vertical dimension while maintaining larger horizontal pixel region sizes, thus resolving the contradiction between pixel density and full well capacity.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

3Device complexity

If image sensing elements and pixel support devices are integrated on the same substrate, then device complexity is reduced, but pixel region size is constrained leading to decreased full well capacity

Engineering Contradiction:

Improveintegration structureVSAvoidfull well capacity

Core Design Contradiction:

Device complexityVSReliability

Solution Approach 1:

The patent divides the image sensor into multiple separate tiers: a first tier containing pixel support devices and a second tier containing image sensing elements. This segmentation allows each tier to be optimized independently, enabling larger pixel regions in the second tier while maintaining high pixel density through the multi-tier architecture.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The patent introduces interconnect structures as intermediaries to electrically couple the pixel support devices on the first tier with the image sensing elements on the second tier. These interconnect structures include conductive vias and wiring that bridge the two tiers, enabling functional integration while maintaining physical separation for optimized pixel region sizing.

Inventive Principle:

Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This configuration improves the full well capacity and performance of the image sensor by maintaining larger pixel regions and allowing for various pixel configurations, enhancing image quality and auto focus functionality.

Implementation Method 1

a pixel region including a photodiode

Methodology Applied

Scientific EffectPhotoelectric effect: Photoelectric Effect

Data Source

PatentUS20240290811A1Image sensor integrated chip structure

Publication Date: 2024.08.29 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

The present disclosure relates to an image sensor integrated chip structure. The image sensor integrated chip structure includes one or more logic devices disposed within a first substrate and coupled to a first interconnect structure on the first substrate. A plurality of pixel support devices are disposed along a first-side of a second substrate and coupled to a second interconnect structure on the second substrate. The first substrate is bonded to the second substrate. A plurality of image sensing elements are disposed within a third substrate in pixel regions respectively including two or more of the plurality of image sensing elements. A plurality of transfer gates and a third interconnect structure are disposed on a first-side of the third substrate. The third interconnect structure includes interconnect wires and vias confined between the first-side of second substrate and the first-side of the third substrate.