Display Substrate Through-Hole Interconnects for Dead Space Reduction

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Solution Overview

Problem

Display devices often have a significant dead space due to the arrangement of electronic components and conductive layers, which complicates the manufacturing process and increases the peripheral area outside the display unit.

Innovation Solution

A display device design featuring a first and second substrate layer with strategically arranged through holes and intermediate conductive layers, along with a barrier layer, that allows for reduced dead space and simplified manufacturing by enabling efficient electrical connections between electronic devices and the display unit, using a method that includes forming specific through holes and conductive layers on the substrate layers and connecting them through the substrate layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If electronic components and conductive layers are arranged in conventional display devices, then electrical connections can be established, but dead space increases and manufacturing complexity increases

Engineering Contradiction:
Improvedead spaceVSAvoidmanufacturing process complexity
Core Design Contradiction:
Area of stationary objectVSDevice complexity

Solution Approach 1:

The patent transitions from planar arrangement of conductive layers to a three-dimensional stacked configuration with through-holes penetrating multiple substrate layers. Intermediate conductive layers are positioned at different vertical levels, enabling electrical connections through the thickness direction rather than only in-plane, thereby reducing dead space while maintaining connection functionality

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

Solution Approach 2:

The patent implements a nested structure where intermediate conductive layers are embedded within through-holes of substrate layers, and barrier layers are positioned within through-holes to surround conductive elements. This nested arrangement consolidates multiple functional layers into a compact vertical stack, reducing overall dead space

Inventive Principle:
Principle #7Nested doll (Nesting)

2Area of stationary object

If multiple through holes and intermediate conductive layers are used to reduce dead space, then electrical connections are achieved, but manufacturing process complexity increases

Engineering Contradiction:
Improvedead spaceVSAvoidmanufacturing process simplicity
Core Design Contradiction:
Area of stationary objectVSEase of manufacture

Solution Approach 1:

The patent performs preliminary actions by pre-forming through-holes in substrate layers before inserting intermediate conductive layers and barrier layers. Adhesive layers are pre-applied to conductive elements to ensure proper positioning and electrical connection during subsequent assembly steps, simplifying the overall manufacturing process despite the multi-layer complexity

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent divides the conductive connection path into segmented sections: first substrate layer with first through-hole, intermediate conductive layer, second substrate layer with second through-hole, and barrier layers. Each segment is independently formed and assembled, allowing for modular manufacturing and quality control while achieving the overall connection goal

Inventive Principle:
Principle #1Segmentation

Data Source

PatentUS11335763B2Display apparatus and method of manufacturing the same
Publication Date: 2022.05.17 SAMSUNG DISPLAY CO LTD
  • US11335763B2 patent drawing
  • US11335763B2 patent drawing
  • US11335763B2 patent drawing

AI summary

A method of manufacturing a display device includes preparing a carrier substrate, forming a first substrate layer on the carrier substrate, forming a first, second, and third through holes in the first substrate layer, forming a first intermediate conductive layer having a first exposed portion and a second exposed portion, forming a second intermediate conductive layer having a third exposed portion, forming a second substrate layer on the first substrate layer to cover the first intermediate conductive layer and the second intermediate conductive layer, forming a fourth through hole in the second substrate layer, forming a wiring on the second substrate layer, separating the first substrate layer from the carrier substrate, arranging a first electronic device on a surface of the first substrate layer, and arranging a second electronic device on the surface of the first substrate layer.