U-Shaped FRAM Bottom Electrode for Higher Capacitor Area
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The semiconductor industry faces challenges in scaling down integrated circuit (IC) manufacturing due to increased complexity and the need for improved processing and manufacturing techniques, particularly in the formation of ferroelectric random access memory (FRAM) cells, where precise dimensions and material thicknesses are critical for performance and reliability.
Innovation Solution
The solution involves a method for fabricating IC structures with FRAM cells that includes forming a bottom electrode layer with a U-shaped configuration over a conductive line, a ferroelectric layer conformally deposited on the electrode, and a top electrode layer, where the effective area between the electrodes is optimized to enhance capacitor performance and reliability, using materials like strontium bismuth tantalite (SBT) and lead zirconate titanate (PZT) for the ferroelectric layer, and copper or tantalum nitride for electrodes, with specific thickness ranges to ensure proper functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If geometry size is decreased to increase functional density, then production efficiency and cost are improved, but processing complexity increases
Solution Approach 1:
The patent segments the bottom electrode into multiple portions (first bottom electrode portion, second bottom electrode portion) with different configurations. The first portion has a U-shaped configuration extending over the first conductive line, while the second portion has a different configuration over the second conductive line. This segmentation allows each portion to be optimized independently for its specific function, enabling scaling while managing processing complexity through modular design.
Solution Approach 2:
The patent applies local quality by giving different electrode configurations to different regions of the device. The bottom electrode has varying thicknesses and shapes at different locations - thicker and U-shaped in some regions, thinner and planar in others. This localized optimization allows the device to maintain performance across different geometric scales, addressing the complexity introduced by scaling while preserving functional density benefits.
2Reliability
If electrode configuration is optimized to increase effective area, then capacitor performance and reliability are improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent transitions from a planar electrode configuration to a three-dimensional U-shaped configuration for the bottom electrode. The electrode extends vertically and horizontally, creating multiple surfaces that contact the ferroelectric layer. This dimensional change increases the effective area without proportionally increasing the footprint, thereby improving reliability while managing manufacturing precision requirements through vertical utilization of space.
Solution Approach 2:
The bottom electrode's U-shaped configuration creates a nested structure where the electrode wraps around and extends over the conductive line. This nesting approach maximizes the effective area within a compact footprint, allowing the electrode to contact the ferroelectric layer at multiple locations (inner surface, outer surface, and top surface) without requiring proportionally larger dimensions, thus balancing reliability improvement with manufacturing precision constraints.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves the effective area of the capacitor and reliability of the FRAM cells by optimizing the electrode configurations and material thicknesses, leading to enhanced performance and process window improvements in IC manufacturing.
Implementation Method 1
a ferroelectric layer conformally deposited on the electrode
Implementation Method 2
using materials like strontium bismuth tantalite (SBT) and lead zirconate titanate (PZT) for the ferroelectric layer
Data Source
AI summary
A method of forming a semiconductor device includes forming an inter-metal dielectric layer over a substrate; forming a first conductive line embedded in the inter-metal dielectric layer; forming a dielectric structure over the inter-metal dielectric layer and the first conductive line; etching the dielectric structure until the first conductive line is exposed; forming a bottom electrode layer on the exposed first conductive line such that the bottom electrode layer has an U-shaped when viewed in a cross section; forming a ferroelectric layer over the bottom electrode layer; forming a top electrode layer over the ferroelectric layer.