Amorphous Semiconductor Threshold Switch Memory Cell
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Solution Overview
Problem
Existing semiconductor memory technologies face challenges in efficiently utilizing amorphous semiconductor threshold switches, particularly in achieving dense memory arrays with rapid conductivity changes without phase changes, and in maintaining programmed states with minimal leakage.
Innovation Solution
A volatile memory array incorporating an amorphous semiconductor threshold switch in series with a select device, such as a conventional N channel MOS transistor, utilizing a chalcogenide alloy that remains in an amorphous state and exhibits rapid electric field-induced conductivity changes, allowing for reversible switching between high and low resistance states based on voltage potentials.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If amorphous semiconductor threshold switches are used in memory arrays, then memory density and speed are improved, but leakage current increases making it difficult to maintain programmed states
Solution Approach 1:
The patent combines an amorphous semiconductor threshold switch with a crystalline semiconductor memory element (such as a phase change memory element) into a single memory cell. The threshold switch provides rapid switching for high-speed operation, while the crystalline element provides stable state retention with minimal leakage. This merging allows the memory cell to achieve both high productivity and low energy loss.
Solution Approach 2:
The memory cell uses a composite structure combining amorphous semiconductor material (for the threshold switch) with crystalline semiconductor material (for the memory element). The amorphous material provides fast switching characteristics, while the crystalline material provides stable, low-leakage state retention. This composite approach resolves the contradiction between speed and leakage by leveraging the complementary properties of different material phases.
2Reliability
If conventional six transistor static random access memory is used, then stability and leakage control are improved, but device size and complexity increase
Solution Approach 1:
The patent merges the threshold switch and memory element into a single integrated cell that can be accessed with fewer transistors than conventional six-transitor SRAM cells. The amorphous threshold switch acts as a selective device that enables or disables access to the memory element, reducing the need for additional access transistors while maintaining stable state retention through the crystalline memory element.
3Quantity of substance
If amorphous to crystalline phase change memory is used, then memory states are stored through phase transitions, but the process requires significant energy and time
Solution Approach 1:
The patent uses a crystalline semiconductor memory element that stores memory states through electrical charge or magnetic properties rather than requiring phase transitions. This approach maintains the ability to store multiple memory states while significantly reducing the energy required for writing and reading operations, as no material phase change is needed.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration enables efficient writing and reading operations with minimal leakage, achieving dense memory arrays comparable in speed to conventional six transistor static random access memory while being significantly smaller in size, and maintaining programmed states with reduced cell size and power consumption.
Implementation Method 1
undergoes rapid, electric field initiated change in electrical conductivity that persists only so long as a holding voltage is present
Implementation Method 2
An amorphous semiconductor threshold switch exhibits S-shaped threshold switch current-voltage characteristics
Data Source
AI summary
A voltage memory switch may be formed of an amorphous semiconductor threshold switch and a select device. The amorphous threshold switch may be latched into one of two different current conducting levels. Then, in some embodiments, a relatively dense memory array can be achieved by maintaining an appropriate bias on the cell to prevent it from losing the programmed state.