Memory-Agnostic Chiplet Architecture for Flexible Memory Access
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Solution Overview
Problem
Traditional chiplet architectures are limited by inflexible memory interfaces, which constrain the usage of chiplets in various applications and increase costs due to decreasing yields for larger integrated circuit chips.
Innovation Solution
A multi-chip module (MCM) architecture that employs a memory-agnostic interface on integrated circuit (IC) chiplets, coupled with a peripheral gearbox chiplet and network-on-chip (NoC) circuitry, allowing for flexible memory access and expanded application capabilities through packet-based signaling protocols and universal die-to-die interfaces.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If traditional chiplet architectures employ large and complex on-chip memory interfaces, then memory access capability is improved, but device complexity and manufacturing cost increase
Solution Approach 1:
The patent extracts the memory interface functionality from the chiplet itself and places it in a separate memory controller located in the package substrate. This separation removes the complex memory interface from the chiplet, simplifying its design while maintaining high memory access capability through dedicated controller hardware in the substrate.
Solution Approach 2:
The patent introduces a memory controller as an intermediary component between the chiplet and the memory device. This mediator handles all complex memory interface operations, allowing the chiplet to access memory with high speed without needing to incorporate complex interface circuitry directly into the chiplet design.
2Speed
If traditional chiplet architectures use specific memory type interfaces, then memory performance is optimized, but adaptability to various memory types decreases
Solution Approach 1:
The patent designs the memory controller with universal functionality to support multiple memory types including DDR, HBM, and other memory technologies. This single universal controller can be configured to work with different memory interfaces, allowing the same chiplet design to be adapted to various memory types without requiring dedicated interface circuitry for each memory type.
Solution Approach 2:
The patent enables the memory controller to dynamically adjust its operating parameters and interface configuration based on the specific memory type being used. By changing control parameters and interface settings rather than hardware architecture, the system achieves both optimized performance for each memory type and broad adaptability across different memory technologies.
3Adaptability or versatility
If larger integrated circuit chips are manufactured, then functionality is increased, but manufacturing yield decreases and cost increases
Solution Approach 1:
The patent segments the complete system into separate functional components: processing chiplets and memory controllers placed in the package substrate. This allows each chiplet to be manufactured independently at optimal sizes for high yield, while the substrate integrates multiple chiplets to achieve the overall system functionality. Complex memory interface functionality is placed in the substrate rather than requiring larger chiplet sizes.
Data Source
AI summary
Semiconductor devices, packaging architectures and associated methods are disclosed. In one embodiment, a multi-chip module (MCM) is disclosed. The MCM includes a common substrate and a first integrated circuit (IC) chiplet disposed on the common substrate. The first IC chiplet includes at least one processing element. A communications fabric switchably couples to the at least one processing element. A peripheral gearbox chiplet (PGC) includes a first port having a second memory-agnostic interface coupled to the first memory-agnostic interface of the first IC chiplet. The PGC includes a second port having a memory interface of a first type and interface conversion circuitry disposed between the second memory-agnostic interface and the memory interface of the first type.