Display Panel Signal and Power Layout Without Wiring Crossovers
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Solution Overview
Problem
Current display panel designs with multiple layers of metal wirings are prone to short circuits, leading to increased costs and manufacturing challenges.
Innovation Solution
The display panel design incorporates a single layer for the grounding signal wiring, driving chip input output signal wiring, and power line, ensuring they do not intersect, thereby preventing short circuits.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If metal wirings are disposed in two or more layers, then wiring functionality is improved, but short circuit risk increases
Solution Approach 1:
The patent transitions from a multi-layer vertical arrangement to a single-layer planar arrangement, using spatial dimensionality change to resolve the contradiction. All wirings (power supply wiring, grounding signal wiring, input output signal wiring) are disposed in the same layer but arranged in different directions, eliminating vertical intersections that cause short circuits while maintaining wiring functionality through directional separation.
2Adaptability or versatility
If multiple layers of metal wirings are used, then signal routing capability is improved, but manufacturing complexity increases
Solution Approach 1:
The patent merges multiple wiring layers into a single layer, combining power supply wiring, grounding signal wiring, and input output signal wiring in the same plane. This merging reduces manufacturing complexity by eliminating layer stacking processes while maintaining signal routing capability through strategic directional arrangement and spacing of different wiring types.
Data Source
AI summary
A display panel is provided, including a grounding signal wiring, driving chips, a driving chip input output signal wiring, and a power line. A grounding signal pin is connected to the grounding signal wiring. The driving chip input output signal wiring is configured to connect a stage-transfer signal input pin and a stage-transfer signal output pin of two adjacent driving chips. The grounding signal wiring, the driving chip input output signal wiring, and the power line are disposed in a same layer and do not intersect with each other.