Backside Wafer Memory Cell Layout for Frontside Routing Space
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Solution Overview
Problem
As semiconductor device dimensions shrink, the frontside of a wafer substrate often lacks sufficient space for all wires, necessitating the formation of passive components and wires on the backside to free up space for wire routing.
Innovation Solution
A method is developed to form memory devices on the backside of a wafer substrate, involving steps like etching a substrate indentation, forming a silicide layer, and constructing memory device components such as electrodes and data-storage dielectric features within this indentation, allowing for efficient wire routing on the frontside.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If device dimensions are shrunk to increase density, then device capacity is improved, but space for wire routing on the frontside becomes insufficient
Solution Approach 1:
The patent moves passive components (memory devices, wires, and interconnects) from the frontside to the backside of the wafer substrate, utilizing the third dimension (depth/vertical space) by forming structures within substrate indentations. This dimensional transition frees up frontside area for wire routing while maintaining high device density through vertical stacking and backside integration.
2Area of stationary object
If passive components are formed on the backside to free up frontside space, then wire routing space is improved, but device structure complexity increases
Solution Approach 1:
The patent segments the wafer substrate into distinct functional regions: the frontside for active circuitry and wire routing, and the backside for passive components (memory devices, capacitors, and interconnects). This spatial segmentation allows independent optimization of each region, simplifying the overall design by separating conflicting requirements.
Solution Approach 2:
The patent forms memory devices and other passive components within substrate indentations, effectively nesting these structures inside the substrate volume. This nesting approach utilizes the substrate's internal space rather than adding external layers, reducing overall structure complexity while achieving high density.
3Area of stationary object
If memory devices are formed in substrate indentations, then space utilization is improved, but manufacturing precision requirements increase
Solution Approach 1:
The patent performs preliminary actions by forming the substrate indentations and memory device structures on the backside before completing the frontside wire routing processes. This sequence allows the indentations to be precisely formed and filled with memory structures while the frontside is still being prepared, reducing the need for high-precision alignment between frontside and backside features.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables the formation of memory devices on the backside, ensuring sufficient space on the frontside for wire routing, even with increased device density, thereby facilitating the integration of complex semiconductor structures.
Implementation Method 1
a bonding layer is formed on the carrier wafer, and the device wafer is bonded to the carrier wafer using the bonding layer
Implementation Method 2
the backside portion of the wafer substrate is etched to form a substrate indentation
Implementation Method 3
a dielectric liner layer is conformally formed over the backside portion of the wafer substrate and in the substrate indentation
Implementation Method 4
a silicide layer is formed over an exposed silicon-containing feature
Data Source
AI summary
A method is provided for forming a memory device on a backside portion of a wafer substrate. In one step, a circuit device is formed on a frontside portion of the wafer substrate. In one step, the wafer substrate is etched to form a substrate indentation that exposes a portion of a circuit device. In one step, a memory device is formed, at least in part, in the substrate indentation.