Semiconductor Interconnection Passivation for Damascene Cleaning

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Solution Overview

Problem

The conventional Damascene process for forming copper interconnections in semiconductor manufacturing often results in metal interconnection material loss during the cleaning process, leading to loose bonding and open circuit issues due to polymer residues left after etching, affecting the interconnection properties and overall IC chip performance.

Innovation Solution

A method involving the formation of a passivation layer on the metal interconnection material using a 1,2,3-benzotriazole solution to protect it from cleaning processes, followed by removal of polymer residues without damaging the metal layer, and subsequent removal of the passivation layer to allow for tight bonding of the metal layer with the conductive layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Object-generated harmful factors

If a cleaning process is performed to remove polymer residues after etching, then the cleaning effectiveness is improved, but metal interconnection material is damaged and lost

Engineering Contradiction:
Improvepolymer residuesVSAvoidmetal interconnection material
Core Design Contradiction:
Object-generated harmful factorsVSLoss of substance

Solution Approach 1:

A passivation layer is formed on the metal interconnection material surface before the cleaning process. This preliminary protective action prevents the cleaning solution from contacting and damaging the metal material, allowing effective removal of polymer residues without material loss.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The passivation layer acts as an intermediary substance between the cleaning solution and the metal interconnection material. It provides a protective barrier that allows the cleaning process to proceed effectively while preventing direct interaction between the cleaning solution and the metal material.

Inventive Principle:
Principle #24Intermediary (Mediator)

2Loss of substance

If the metal interconnection material is protected during cleaning, then the material integrity is improved, but the cleaning effectiveness may be reduced

Engineering Contradiction:
Improvemetal interconnection materialVSAvoidpolymer residues
Core Design Contradiction:
Loss of substanceVSObject-generated harmful factors

Solution Approach 1:

The passivation layer is applied before cleaning to protect the metal surface. After cleaning removes the polymer residues, the passivation layer is removed to restore full surface access, ensuring both material protection during cleaning and effective residue removal.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The passivation layer is temporarily applied during the cleaning process and then removed afterward. This temporary protective measure allows effective cleaning while preventing material damage, and the layer is discarded after serving its protective function.

Inventive Principle:
Principle #34Discarding and recovering

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach prevents metal loss and ensures stable, defect-free interconnections by maintaining the integrity of the metal layer during cleaning, enhancing the performance and yield of the semiconductor structure.

Implementation Method 1

forming a passivation layer for protecting the portion of the conductive layer on a surface of the portion of the conductive layer on the bottom of the opening using a passivation solution

Methodology Applied
Scientific EffectPassivation:

Implementation Method 2

cleaning inner surface of the opening using a cleaning solution not reacting with the passivation layer

Methodology Applied
Scientific EffectChemical cleaning:

Data Source

PatentUS9305833B2Semiconductor structures and fabrication method thereof
Publication Date: 2016.04.05 SEMICON MFG INT (SHANGHAI) CORP
  • US9305833B2 patent drawing
  • US9305833B2 patent drawing
  • US9305833B2 patent drawing

AI summary

A method is provided for fabricating a semiconductor structure. The method includes providing a substrate; and forming a conductive layer in one surface of the substrate. The method also includes forming a dielectric layer on the surface of the substrate; and forming an opening exposing a portion of the conductive layer in the dielectric layer. Further, the method includes forming a passivation layer for protecting the portion of the conductive layer on a surface of the portion of the conductive layer on the bottom of the opening using a passivation solution; and cleaning inner surface of the opening using a cleaning solution not reacting with the passivation layer. Further, the method also includes removing the passivation layer; and forming a metal layer connecting with the conductive layer in the opening.