Cut Metal Gate Etching With Tapered Openings for Void Reduction
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Solution Overview
Problem
The semiconductor industry faces challenges in improving processing and manufacturing of ICs due to increased complexity and void formation in isolation materials during the cut metal gate process.
Innovation Solution
A method involving a main etch step and a final breakthrough etch step is employed to form openings in the gate electrode, using a pulsing scheme for the etching process to control the etching angle and minimize void formation in the isolation material.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If a single etch process is used to form openings in the gate electrode, then the process is simple and fast, but voids form in the isolation material and the opening profile is poor
Solution Approach 1:
The etch process is divided into two distinct steps: a main etch step that forms the opening through the gate electrode, and a breakthrough etch step that completes the opening through the isolation material. This segmentation allows each step to be optimized independently, with the main etch creating a tapered profile and the breakthrough etch completing the opening with minimal void formation.
Solution Approach 2:
The main etch step performs preliminary action by creating a tapered opening profile through the gate electrode before the breakthrough etch step. This preliminary tapered structure guides the subsequent dielectric refill process and prepares the opening for complete formation with minimal voids.
2Productivity
If the etching process continues without interruption to complete the opening, then the process is efficient, but voids form in the isolation material
Solution Approach 1:
The continuous etching process is segmented into two distinct phases: the main etch step that etches through the gate electrode to a predetermined depth, and the breakthrough etch step that completes the opening through the isolation material. This segmentation prevents void formation by controlling the etching depth and profile at each stage.
Solution Approach 2:
While segmented into two steps, the etching process maintains continuity of useful action by seamlessly transitioning from the main etch step to the breakthrough etch step without requiring intermediate cleaning or repositioning, thus preserving efficiency while improving precision.
3Reliability
If the gate electrode openings are not properly formed, then the process is simple, but dielectric material refill is poor and device yield decreases
Solution Approach 1:
The main etch step performs preliminary action by creating a tapered opening profile with specific geometric characteristics that are optimized for subsequent dielectric refill. This preliminary tapered structure ensures proper capillary action and material flow during the refill process, directly improving device yield.
Solution Approach 2:
The etch process parameters are changed between the two steps: the main etch uses parameters optimized for creating a tapered profile through the gate electrode, while the breakthrough etch uses parameters optimized for completing the opening through the isolation material with minimal void formation, ensuring optimal conditions for dielectric refill.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a tapered profile of the openings, reducing void size and improving the refill of dielectric material, which enhances device performance and yield by preventing missing metal gates and ensuring proper isolation between metal gates.
Implementation Method 1
performing a first etch process on the gate electrode by applying a first source power and a first bias power with a first pulsing scheme
Implementation Method 2
depositing a gate electrode over the plurality of fins
Data Source
AI summary
A method for forming a semiconductor device structure is described. In some embodiments, the method includes forming a gate electrode, forming a mask structure over the gate electrode, patterning the mask structure to form an opening, and performing a first etch process on the gate electrode by applying a first source power and a first bias power with a first pulsing scheme. The first bias power has a first frequency to control etching along a lateral direction. The method further includes performing a second etch process on the mask structure exposed within the opening by applying a second source power and a second bias power with a second pulsing scheme, and the second bias power has a second frequency to control etching along a vertical direction. The first and second frequencies are substantially different.