Ferromagnetic-Core Inductor Structure for Stress-Tolerant RDL Integration
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Solution Overview
Problem
The integration of multiple semiconductor devices in wafer-level packaging poses challenges for miniaturization, higher speed, and reduced transmission and insertion losses, as existing techniques lack effective creative packaging and assembling methods.
Innovation Solution
The method involves a semiconductor device manufacturing process using a carrier with semiconductor dies and a redistribution structure that includes dielectric layers, conductive traces, and vias, along with a ferromagnetic-core inductor design featuring a buffer layer, etch stop layer, and core material layer to enhance electrical connections and mechanical stress dissipation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If traditional wafer-level packaging techniques are used, then manufacturing simplicity is maintained, but integration density and electrical performance deteriorate
Solution Approach 1:
The patent implements nested packaging by placing encapsulated semiconductor dies within a lead frame cavity, then encapsulating the entire assembly in a second encapsulant. This multi-level nesting approach achieves high integration density while maintaining manufacturability through standardized processes.
Solution Approach 2:
The patent transitions from planar wafer-level integration to three-dimensional packaging by stacking encapsulated dies vertically within the lead frame. This vertical arrangement dramatically increases integration density without proportionally increasing the package footprint, resolving the contradiction between density and complexity.
2Volume of moving object
If miniaturization is pursued, then device size is reduced, but transmission loss and insertion loss increase
Solution Approach 1:
By arranging conductive traces in multiple vertical layers within the encapsulant rather than spreading them horizontally, the patent reduces the horizontal trace length and associated resistance. This vertical stacking maintains electrical performance while minimizing package size.
Solution Approach 2:
The patent combines multiple functions into integrated structures, such as forming both mechanical support and electrical interconnection functions within the same lead frame and encapsulant assembly, reducing the number of separate components and minimizing overall package volume without compromising signal integrity.
3Speed
If higher speed performance is achieved, then signal transmission quality improves, but manufacturing complexity increases
Solution Approach 1:
The patent uses vertical stacking of conductive traces across multiple layers to create direct, short signal paths between input and output terminals. This three-dimensional interconnection topology reduces signal path length and parasitic effects, enabling high-speed transmission while using standard multi-layer PCB fabrication techniques.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables efficient integration of semiconductor devices with improved electrical performance and reliability by reducing mechanical stress and enhancing manufacturing yield, while allowing for the formation of inductors within the redistribution structure for better integration.
Implementation Method 1
The core includes a core material layer and at least one base layer selected from a buffer layer, an etch stop layer, or both a buffer layer and an etch stop layer... The core material layer includes a ferromagnetic material
Data Source
AI summary
An inductor includes a core and a conductive spiral wound around the core. The core includes a buffer layer, an etch stop layer, and a core material layer sequentially stacked. The core material layer includes a ferromagnetic material. A total area of a vertical projection of the core material layer is smaller than an area occupied by the etch stop layer. The vertical projection of the core material layer falls entirely on the etch stop layer. The etch stop layer horizontally protrudes with respect to the core material layer.