Memory Cell Electrode Resistivity Layout for Overshoot Current Control

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Solution Overview

Problem

Semiconductor devices face challenges in efficiently driving memory cells located far from peripheral circuit regions due to excessive current flow, leading to operation failures from overshooting currents.

Innovation Solution

The semiconductor device incorporates a substrate with distinct cell regions and conductive lines, where memory cells in the first cell region have higher resistive electrode layers compared to those in the second cell region, facilitating controlled voltage/current transfer and preventing excessive current flow.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Area of stationary object

If memory cells are disposed far from peripheral circuit regions to increase storage capacity, then the cell region area is improved, but excessive current flow occurs leading to operation failures

Engineering Contradiction:
Improvecell region areaVSAvoidoperation reliability
Core Design Contradiction:
Area of stationary objectVSReliability

Solution Approach 1:

The patent applies local quality by differentiating the electrode layer resistivity based on spatial location. Memory cells in the first cell region (closer to peripheral circuits) have electrode layers with first resistivity, while memory cells in the second cell region (farther from peripheral circuits) have electrode layers with second resistivity. This local differentiation allows the device to handle the excessive current flow issue specifically in regions where it occurs, enabling larger cell regions while maintaining operation reliability.

Inventive Principle:
Principle #3Local quality

2Device complexity

If uniform electrode layers are used across all memory cells, then manufacturing complexity is reduced, but current control precision deteriorates due to varying distances from peripheral circuits

Engineering Contradiction:
Improveelectrode layer structure complexityVSAvoidcurrent control precision
Core Design Contradiction:
Device complexityVSManufacturing precision

Solution Approach 1:

The patent implements local quality by creating two distinct types of electrode layers with different resistivities tailored to specific spatial regions. This allows precise current control for memory cells at different distances from peripheral circuits, addressing the current control precision issue while maintaining a relatively simple manufacturing process through the use of two standardized electrode layer types.

Inventive Principle:
Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design ensures reliable operation of memory cells by allowing controlled voltage/current transfer to memory cells, preventing excessive current flow and ensuring efficient driving, particularly for cells farther from peripheral circuit regions.

Implementation Method 1

the first electrode layer further includes a first dopant that increases a resistivity of the conductive material

Methodology Applied
Scientific EffectDoping: Dopants

Implementation Method 2

the first resistance layer further includes a dopant that increases a resistivity of the resistance material

Methodology Applied
Scientific EffectDoping: Dopants

Data Source

PatentUS20230413699A1Semiconductor device and method for fabricating the same
Publication Date: 2023.12.21 SK HYNIX INC
  • US20230413699A1 patent drawing
  • US20230413699A1 patent drawing
  • US20230413699A1 patent drawing

AI summary

A semiconductor device may include: a substrate including a peripheral circuit region and a cell region having a first cell region and a second cell region, the second cell region being farther from the peripheral circuit region than the first cell region; a plurality of memory cells disposed at intersection regions between first conductive lines and second conductive lines, respectively, the memory cells including a first memory cell disposed in the first cell region and a second memory cell disposed in the second cell region, wherein a first electrode layer of the first memory cell and a second electrode layer of the second memory cell include a conductive material, and wherein the first electrode layer further includes a first dopant that increases a resistivity of the conductive material.