IGBT ESD Protection Structure With Low Capacitance Clamping
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Solution Overview
Problem
Existing ESD protection devices in data transmission systems face challenges with high trigger voltages, snapback voltage, and high capacitance, which can lead to component damage during electrostatic discharge events.
Innovation Solution
An insulated-gate bipolar transistor (IGBT) device with a specific doping structure and antiparallel diode configuration that reduces capacitance and allows for tunable breakdown voltage, functioning as a stand-alone ESD protection or trigger device, while avoiding snapback and maintaining high current density.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If a MOSFET is used for ESD protection, then the device structure is simple, but the capacitance is very high due to its size and gate oxide
Solution Approach 1:
The device is segmented into two distinct functional parts: a bipolar transistor structure for low-capacitance operation and a MOSFET gate structure for voltage control. The bipolar structure (with emitter, base, and collector regions) handles the ESD protection function with low capacitance, while the MOSFET gate provides insulated voltage control without contributing significantly to the overall capacitance. This segmentation allows each part to optimize its own characteristics without compromising the other.
2Ease of operation
If the Gate terminal is connected to one of the terminals in a two-pin ESD protection device, then the device can function as ESD protection, but the capacitance increases further due to the thin gate oxide
Solution Approach 1:
The gate oxide layer acts as an intermediary between the control voltage applied to the gate and the bipolar transistor structure. This thin insulating layer allows voltage control of the bipolar device without creating a low-impedance capacitive path to ground. The gate oxide mediates the interaction between the control signal and the power handling structure, enabling voltage-controlled ESD protection with minimal capacitance contribution from the gate structure.
3Quantity of substance
If SCR is used for ESD protection, then the clamping voltage is low due to deep snap-back, but the trigger voltage is high especially when low capacitance is needed
Solution Approach 1:
The device uses parameter changes in the bipolar transistor structure to control the turn-on characteristics. By adjusting the doping concentrations, junction depths, and geometric dimensions of the emitter, base, and collector regions, the trigger voltage can be optimized to be lower than conventional SCR devices. The parameter changes in the bipolar structure enable controlled snap-back behavior that provides low clamping voltage while maintaining acceptable trigger voltage levels for ESD protection applications.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The IGBT device effectively dissipates electrostatic discharge with low trigger voltage and reduced capacitance, preventing component damage and enhancing the reliability of data transmission systems.
Implementation Method 1
The low capacitance of the pair of antiparallel diode devices hides the high capacitance of the gate oxide of the gate structure
Implementation Method 2
The IGBT device effectively dissipates electrostatic discharge with low trigger voltage and reduced capacitance
Data Source
Figure 1
Figure 2A
Figure 2B
AI summary
An insulated-gate bipolar transistor device comprising: a first region doped with a first type of charge carriers; a second region doped with a second type of charge carriers different from the first type of charge carriers; a third region doped with the first type of charge carriers; a fourth region doped with the second type of charge carriers; a first, emitter terminal electrically connected with the first region and a second, collector terminal electrically connected with the third region and the fourth region; and a gate structure disposed on the third region with one end adjacent to the second region and with another end adjacent the fourth region; as well as a diode structure having a first diode structure terminal electrically connected with the collector terminal and a second diode structure terminal electrically connected with the gate terminal of the gate structure.