Memory Peripheral Transistor Layout With Unequal Gate Oxides
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Solution Overview
Problem
Current semiconductor memory devices face challenges in increasing integration density while maintaining performance and reliability, particularly in the design of transistors with gate insulating layers of different thicknesses on a single active region.
Innovation Solution
A semiconductor memory device is designed with a cell structure and a peripheral circuit structure, where the cell structure includes gate electrodes, a channel structure, and a bit line, and the peripheral circuit structure features active regions with gate structures having different gate insulating layer thicknesses, ensuring the source/drain regions maintain equal depth despite the thickness differences.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If gate insulating layers of different thicknesses are implemented on one active region to improve integration density, then the integration density is improved, but the manufacturing precision and reliability are compromised due to difficulty in maintaining equal source/drain region depth
Solution Approach 1:
The active region is segmented into multiple regions (first active region and second active region) with different gate insulating layer thicknesses. This allows each segment to have optimized gate characteristics while maintaining uniform source/drain region formation through separate processing steps for each segment.
Solution Approach 2:
Different gate insulating layer thicknesses are applied to different local regions of the active area. The first gate insulating layer has a first thickness in the first active region, while the second gate insulating layer has a second thickness in the second active region, allowing localized optimization of transistor performance.
2Productivity
If multiple gate structures with different gate insulating layer thicknesses are formed on the same active region, then the integration density is improved, but the device complexity increases
Solution Approach 1:
The active region is divided into distinct first and second active regions, each with its own gate structure and gate insulating layer. This segmentation simplifies the formation process compared to attempting to create multiple gate structures on a single continuous active region, as each segmented region can be processed independently.
Data Source
AI summary
A semiconductor memory device comprises a cell structure and a peripheral circuit structure electrically connected to the cell structure. The peripheral circuit structure comprises an active region, a first gate structure comprising a first gate insulating layer intersecting the active region and in contact with the active region, a second gate structure comprising a second gate insulating layer spaced apart from the first gate structure, and in contact with the active region, and a source/drain region between the first gate structure and the second gate structure. A thickness of the first gate insulating layer is less than a thickness of the second gate insulating layer. The source/drain region comprises a first region adjacent to the first gate structure and a second region adjacent to the second gate structure. A depth of the first region is equal to a depth of the second region.