Stacked Memory Chip Package With Mixed Channel Length Transistors
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Solution Overview
Problem
As feature sizes of memory cells approach the processing lower limit, traditional 2D or planar NAND flash memory density reaches an upper limit, making it challenging and expensive to manufacture, prompting the development of 3D NAND structures to improve memory density.
Innovation Solution
A chip-package structure is developed, comprising multiple stacked chips with different channel lengths for transistors, including a peripheral circuit chip with CMOS transistors, a column decoder and power management chip with bipolar and DMOS transistors, and a control circuit chip with CMOS transistors, allowing for different operating voltages and modularized circuit fabrication.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If 2D or planar NAND flash memory is used, then manufacturing process is simpler, but memory density reaches an upper limit
Solution Approach 1:
The patent transitions from 2D planar NAND flash to 3D vertically stacked NAND structure, arranging memory cells in multiple layers along the vertical direction. This dimensional change enables significantly higher memory density by utilizing the third dimension (height) rather than only the planar area, while maintaining compatibility with existing semiconductor manufacturing processes through vertical epitaxial growth and stacking techniques
2Quantity of substance
If feature sizes of memory cells are reduced to increase density, then memory density improves, but manufacturing becomes challenging and expensive
Solution Approach 1:
Instead of continuing to scale down feature sizes in the 2D plane which approaches physical and manufacturing limits, the patent grows memory cells vertically in the third dimension through controlled epitaxial growth. This allows memory density to increase by stacking multiple layers (e.g., 32-layer, 64-layer, or 128-layer structures) while maintaining larger, more manufacturable feature sizes in each individual layer, thus avoiding the manufacturing challenges and costs associated with extreme miniaturization
Solution Approach 2:
The patent changes the growth parameter from lateral expansion to vertical accumulation. By controlling the number of stacked layers, the thickness of each layer, and the composition gradients during vertical epitaxial growth, the patent achieves high memory density without requiring sub-10nm feature sizes that would demand expensive and complex manufacturing equipment and processes
3Ease of manufacture
If all chips use the same transistor channel length, then fabrication process is simpler, but operating voltage requirements are not optimized
Solution Approach 1:
The patent implements different transistor channel lengths in different functional blocks within the same chip. Specifically, peripheral circuit transistors have a first channel length optimized for their switching and logic functions, while memory cell transistors have a second channel length optimized for charge storage and retention. This local differentiation allows each circuit block to operate at its optimal voltage level, improving overall system efficiency and performance while maintaining a unified fabrication process that can accommodate multiple channel length specifications
Data Source
AI summary
According to one aspect of the present disclosure, a chip-package structure is provided. The chip-package structure may include a first chip. The first chip may include at least a peripheral circuit associated with a first transistor. The chip-package structure may include a second chip. The second chip may include at least a column decoder associated with a second transistor. The chip-package structure may include a third chip. The third chip may include at least a control circuit associated with a third transistor. The first chip, the second chip, and the third chip may form a stacked structure. A first channel length of the first transistor, a second channel length of the second transistor, and a third channel length of the third transistor may be different.